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专利名称：Wafer-level die to package and die to die
interconnects suspended over integratedheat sinks
发明人：Florian G. Herrault,Melanie S.
Yajima,Alexandros Margomenos,MiroslavMicovic
申请号：US14720619申请日：20150522公开号：US09385083B1公开日：20160705
专利附图：
摘要：An interconnect for electrically coupling pads formed on adjacent chips or onpackaging material adjacent the chips, with an electrically conductive heat sink beingdisposed between the pads, the interconnect comprising a metallic membrane layerdisposed between two adjacent pads and disposed or bridging over the electricallyconductive heat sink so as to avoid making electrical contact with the electricallyconductive heat sink. An electroplated metallic layer is disposed on the metallicmembrane layer. Fabrication of interconnect permits multiple interconnects to beformed in parallel using fabrication techniques compatible with wafer level fabrication ofthe interconnects. The interconnects preferably follow a smooth curve to electricallyconnect adjacent pads and following that smooth curve they bridge over the interveningelectrically conductive heat sink material in a predictable fashion.
申请人：HRL Laboratories, LLC
地址：Malibu CA US
国籍：US
代理机构：Ladas & Parry
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