ATF16V8B_05资料

Features

•Industry-standard Architecture

–Emulates Many 20-pin PALs®

–Low-cost Easy-to-use Software Tools

•High-speed Electrically-erasable Programmable Logic Devices

–10 ns Maximum Pin-to-pin Delay •Several Power Saving Options

DeviceICC, StandbyICC, ActiveATF16V8B50 mA55 mAATF16V8BQ35 mA40 mAATF16V8BQL

5 mA

20 mA

•CMOS and TTL Compatible Inputs and Outputs–Input and I/O Pull-up Resistors•

Advanced Flash Technology–Reprogrammable–100% Tested

•

High-reliability CMOS Process–20 Year Data Retention–100 Erase/Write Cycles–2,000V ESD Protection–200 mA Latchup Immunity

•Commercial, and Industrial Temperature Ranges

•Dual-in-line and Surface Mount Packages in Standard Pinouts•PCI-compliant

•

Green Package Options (Pb/Halide-free/RoHS Compliant) Available

1.Description

The ATF16V8B is a high-performance CMOS (electricallyerasable) programmablelogic device (PLD) that utilizes Atmel’s proven electrically-erasable Flash memorytechnology. All speed ranges are specified over the full 5V ± 10% range for industrialtemperature ranges, and 5V ± 5% for commercial temperature ranges.

Several low-power options allow selection of the best solution for various types ofpower-limited applications. Each of these options significantly reduces total systempower and enhances system reliability.

The ATF16V8Bs incorporate a superset of the generic architectures, which allowsdirect replacement of the 16R8 family and most 20-pin combinatorial PLDs. Eight out-puts are each allocated eight product terms. Three different modes of operation,configured automatically with software, allow highly complex logic functions to berealized.

High-performance EEPLDATF16V8BATF16V8BQATF16V8BQL 03J–PLD–7/05元器件交易网www.cecb2b.com

Figure 1-1.Block Diagram

2.Pin Configurations

Table 2-1.

Pin NameCLKII/OOEVCC

Pin Configurations (All Pinouts Top View)

FunctionClockLogic InputsBi-directional BuffersOutput Enable+5V Supply

Figure 2-1.

I/CLKI1I2I3I4I5I6I7I8GNDTSSOP

12345671020191817161514131211VCCI/OI/OI/OI/OI/OI/OI/OI/OI9/OEFigure 2-2.DIP/SOIC

I/CLKI1I2I3I4I5I6I7I8GND12345671020191817161514131211VCCI/OI/OI/OI/OI/OI/OI/OI/OI9/OEFigure 2-3.PLCC

I2I1I/CLKVCCI/O3212019I8GNDI9/OEI/OI/O910111213I3I4I5I6I7456781817161514I/OI/OI/OI/OI/O2

ATF16V8B/BQ/BQL

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ATF16V8B/BQ/BQL

3.Absolute Maximum Ratings*

Temperature Under Bias.................................-55oC to +125oCStorage Temperature......................................-65oC to +150oCVoltage on Any Pin with

Respect to Ground.......................................-2.0 V to +7.0 V(1)Voltage on Input Pins with Respect to Ground

During Programming...................................-2.0 V to +14.0 V(1)Programming Voltage with

Respect to Ground.....................................-2.0 V to +14.0 V(1)

*NOTICE:

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Note:

1.Minimum voltage is -0.6V DC, which may under-shoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC+ 0.75V DC, which may overshoot to 7.0V for pulses of less than 20 ns.

4.DC and AC Operating Conditions

Commercial

Operating Temperature (Ambient)VCC Power Supply

0oC - 70oC5V ± 5%

Industrial-40oC - 85oC5V ± 10%

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4.1DC Characteristics

ParameterInput or I/O Low Leakage CurrentInput or I/O HighLeakage Current

Condition0 ≤ VIN ≤ VIL(Max)3.5 ≤ VIN ≤ VCC

B-10

VCC = Max, VIN = Max, Outputs Open

B-15B-15BQ-10BQL-15BQL-15B-10

VCC = Max, Outputs Open, f = 15 MHz

B-15B-15BQ-10BQL-15BQL-15

Com.Ind.Com.Ind.Com.Com.Ind.Com.Ind.Com.Ind.Com.Com.Ind.

55555050355560605555402020

Min

Typ-35

Max-1001085957580551015901008595553540-130

-0.52.0

VIN = VIH or VIL,VCC = MinVIN = VIH or VIL,VCC = Min

IOL = -24 mACom., Ind.IOH = -4.0 mA

2.4

0.8VCC+0.750.5

UnitsµAµAmAmAmAmAmAmAmAmAmAmAmAmAmAmAmAVVVV

SymbolIILIIH

ICC

Power Supply Current, Standby

ICC2

Clocked Power Supply Current

IOS(1)VILVIHVOLVOHNote:

Output Short Circuit CurrentInput Low VoltageInput High VoltageOutput High VoltageOutput High Voltage

VOUT = 0.5 V

1.Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.

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4.2

AC Waveforms(1)

Note:

1.Timing measurement reference is 1.5V. Input AC driving levels are 0.0V 3.0V, unless otherwise

specified.

4.3

AC Characteristics(1)

-10

-15

Max10

Min3

Max15

Units nsnsnsnsnsnsns

455062

3221.5

15151515

MHzMHzMHznsnsnsns

Parameter

Input or Feedback to Non-Registered OutputClock to FeedbackClock to OutputInput or Feedback Setup TimeHold TimeClock PeriodClock Width

External Feedback 1/(tS + tCO)

27.50126

687483

3221.5

10101010

8 outputs switching

Min3

SymboltPDtCFtCOtStHtPtW

67

2120168

810

fMAXInternal Feedback 1/(tS + tCF)No Feedback 1/(tP)

tEAtERtPZXtPXZNote:

Input to Output Enable — Product TermInput to Output Disable — Product TermOE pin to Output EnableOE pin to Output Disable1.See ordering information for valid part numbers and speed grades.

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4.4

4.4.1

Input Test Waveforms

Input Test Waveforms and Measurement Levels

tR, tF < 5 ns (10% to 90%)

4.4.2

Output Test Loads (Commercial)

CL includes Test fixture and Probe capacitance

4.5Pin Capacitance

Table 4-1.

CINCOUTNote:

Pin Capacitance (f = 1 MHz, T = 25°C(1))

Typ56

Max88

UnitspFpF

ConditionsVIN = 0VVOUT = 0V

1.Typical values for nominal supply voltage. This parameter is only sampled and is not 100%

tested.

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4.6

Power-up Reset

The registers in the ATF16V8Bs are designed to reset during power-up. At a point delayedslightly from VCC crossing VRST, all registers will be reset to the low state. As a result, the regis-tered output state will always be high on power-up.

This feature is critical for state machine initialization. However, due to the asynchronous natureof reset and the uncertainty of how VCC actually rises in the system, the following conditions arerequired:

1.The VCC rise must be monotonic,

2.After reset occurs, all input and feedback setup times must be met before driving the

clock pin high, and3.The clock must remain stable during tPR.Figure 4-1.

Power-up Reset Waveforms

Table 4-2.

ParametertPRVRST

Power-up Reset Parameters

DescriptionPower-upReset TimePower-upReset Voltage

Typ6003.8

Max1,0004.5

UnitsnsV

4.7Preload of Registered Outputs

The ATF16V8B’s registers are provided with circuitry to allow loading of each register with eithera high or a low. This feature will simplify testing since any state can be forced into the registersto control test sequencing. A JEDEC file with preload is generated when a source file with vec-tors is compiled. Once downloaded, the JEDEC file preload sequence will be done automaticallyby most of the approved programmers after the programming.

5.Security Fuse Usage

A single fuse is provided to prevent unauthorized copying of the ATF16V8B fuse patterns. Onceprogrammed, fuse verify and preload are inhibited. However, the -bit User Signature remainsaccessible.

The security fuse should be programmed last, as its effect is immediate.

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6.Electronic Signature Word

There are bits of programmable memory that are always available to the user, even if thedevice is secured. These bits can be used for user-specific data.

7.Programming/Erasing

Programming/erasing is performed using standard PLD programmers. See CMOS PLD Pro-gramming Hardware and Software Support for information on software/programming.

8.Input and I/O Pull-ups

All ATF16V8B family members have internal input and I/O pull-up resistors. Therefore, when-ever inputs or I/Os are not being driven externally, they will float to VCC. This ensures that alllogic array inputs are at known states. These are relatively weak active pull-ups that can easilybe overdriven by TTL-compatible drivers (see input and I/O diagrams below).Figure 8-1.

Input Diagram

Figure 8-2.I/O Diagram

9.Functional Logic Diagram Description

The Logic Option and Functional Diagrams describe the ATF16V8B architecture. Eight config-urable macrocells can be configured as a registered output, combinatorial I/O, combinatorialoutput, or dedicated input.

The ATF16V8B can be configured in one of three different modes. Each mode makes theATF16V8B look like a different device. Most PLD compilers can choose the right mode automat-ically. The user can also force the selection by supplying the compiler with a mode selection.The determining factors would be the usage of register versus combinatorial outputs and dedi-cated outputs versus outputswith output enable control.

The ATF16V8B universal architecture can be programmed to emulate many 20-pin PALdevices. These architectural subsets can be found in each of the configuration modes described

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in the following pages. The user can download the listed subset device JEDEC programming fileto the PLD programmer, and the ATF16V8B can be configured to act like the chosen device.Check with your programmer manufacturer for this capability.

Unused product terms are automatically disabled by the compiler to decrease power consump-tion. A security fuse, when programmed, protects the content of the ATF16V8B. Eight bytes (fuses) of User Signature are accessible to the user for purposes such as storing project name,part number, revision, or date. The User Signature is accessible regardless of the state of thesecurity fuse.

10.Software Support

Atmel-WinCUPL is a free tool, available on Atmel’s web site and can be used to design in allmembers of the Atmel ATF16V8B family of SPLDs. Table 10-1 lists popular compilers with theappropriate device mnemonicsTable 10-1.

Compiler Mode Selection

Registered

ABEL, Atmel-ABELCUPL, Atmel-WinCUPLLOG/iCOrCAD-PLDPLDesignerTango-PLDNote:

P16V8RG16V8MSGAL16V8_R(1)“Registered”P16V8RG16V8R

ComplexP16V8CG16V8MAGAL16V8_C7(1)“Complex”P16V8CG16V8C

SimpleP16V8ASG16V8ASGAL16V8_C8(1)“Simple”P16V8CG16V8AS

Auto SelectP16V8G16V8GAL16V8GAL16V8AP16V8AG16V8

1.Only applicable for version 3.4 or lower.

11.Macrocell Configuration

Software compilers support the three different OMC modes as different device types. Most com-pilers have the ability to automatically select the device type, generally based on the registerusage and output enable (OE) usage. Register usage on the device forces the software tochoose the registered mode. All combinatorial outputs with OE controlled by the product termwill force the software to choose the complex mode. The software will choose the simple modeonly when all outputs are dedicated combinatorial without OE control. The different device typescan be used to override the automatic device selection by the software. For further details, referto the compiler software manuals.

When using compiler software to configure the device, the user must pay special attention to thefollowing restrictions in each mode.

In registered mode pin 1 and pin 11 are permanently configuredas clock and output enable,respectively. These pins cannot be configured as dedicated inputs in the registeredmode.In complex mode pin 1 and pin 11 become dedicated inputs and use the feedback paths of pin19 and pin 12 respectively. Because of this feedback path usage, pin 19 and pin 12 do not havethe feedback option in this mode.

In simple mode all feedback paths of the output pins are routed via the adjacent pins. In doingso, the two inner most pins (pins 15 and 16) will not have the feedback option as these pins arealways configured as dedicated combinatorial output.

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11.1ATF16V8B Registered Mode

PAL Device Emulation/PAL Replacement. The registered mode is used if one or more regis-ters are required. Each macrocell can be configured as either a registered or combinatorialoutput or I/O, or as an input. For a registered output or I/O, the output is enabled by the OE pin,and the register is clocked by the CLK pin. Eight product terms are allocated to the sum term.For a combinatorial output or I/O, the output enable is controlled by a product term, and sevenproduct terms are allocated to the sum term. When the macrocell is configured as an input, theoutput enable is permanently disabled.

Any register usage will make the compiler select this mode. The following registered devicescan be emulated using this mode:16R8 16RP8 16R6 16RP6 16R4 16RP4

Figure 11-1.Registered Configuration for Registered Mode(1)(2)

Notes:

1.Pin 1 controls common CLK for the registered outputs. Pin 11 controls common OE for the reg-istered outputs.Pin 1 and Pin 11 are permanently configuredas CLK and OE.2.The development software configures all the architecture control bits and checks for proper pin

usage automatically.

Figure 11-2.Combinatorial Configuration for Registered Mode(1)(2)

Notes:1.Pin 1 and Pin 11 are permanently configured as CLK and OE.2.The development software configures all the architecture control bits and checks for proper pin

usage automatically.

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Figure 11-3.Registered Mode Logic Diagram

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11.2ATF16V8B Complex Mode

PAL Device Emulation/PAL Replacement. In the complex mode, combinatorial output and I/Ofunctions are possible. Pins 1 and 11 are regular inputs to the array. Pins 13 through 18 have pinfeedback paths back to the AND-array, which makes full I/O capability possible. Pins 12 and 19(outermost macrocells) are outputs only. They do not have input capability. In this mode, eachmacrocell has seven product terms going to the sum term and one product term enabling theoutput.

Combinatorial applications with an OE requirement will make the compiler select this mode. Thefollowing devices can be emulated using this mode: 16L8 16H8 16P8

Figure 11-4.Complex Mode Option

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Figure 11-5.Complex Mode Logic Diagram

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11.3ATF16V8B Simple Mode

PAL Device Emulation/PAL Replacement. In the Simple Mode, 8 product terms are allocatedto the sum term. Pins 15 and 16 (center macrocells) are permanently configured as combinato-rial outputs. Other macrocells can be either inputs or combinatorial outputs with pin feedback tothe AND-array. Pins 1 and 11 are regularinputs.

The compiler selects this mode when all outputs are combinatorial without OE control. The fol-lowing simple PALs can be emulated using this mode: 10L8 10H8 10P812L6 12H6 12P6 14L4 14H4 14P4 16L2 16H2 16P2Figure 11-6.Simple Mode Option

Note:* Pins 15 and 16 are always enabled.

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Figure 11-7.Simple Mode Logic Diagram

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12.Test Characterization Data

SUPPLYCURRENTvs.INPUTFREQUENCY75SUPPLYCURRENTvs.INPUTFREQUENCY75ATF16V8BL/BQL (VCC= 5V, TA = 25C)ATF16V8BATF16V8B/BQ (VCC= 5V, TA = 25C)ATF16V8BICCmA50ICCmA5025ATF16V8BQLATF16V8BQ25002040608010000255075100FREQUENCY (MHz)FREQUENCY (MHz)SUPPLYCURRENTvs.SUPPLYVOLTAGE65ATF16V8B/BQ(TA=25C)ATF16V8BICCmA5545ATF16V8BQ35254.504.755.005.255.50SUPPLYVOLTAGE(V)OUTPUTSOURCECURRENT-10-12vs.SUPPLYVOLTAGE(TA=25C)IOHmA-14-16-18-20-22-244.54.74.95.15.35.5SUPPLYVOLTAGE(V)16

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ATF16V8B/BQ/BQLNORMALIZEDTPDvs.SUPPLY VOLTAGE (TA=25°C)1.3NO1.15RMATF16V8B/BQ1TATF16V8BQLP0.85D0.74.504.755.005.255.50SUPPLY VOLTAGE (V)vs.NORMALIZEDSUPPLYVOLTAGE(TA=25°C)TCO1.3NO1.15RATF16V8B/BQM1TATF16V8BQLC0.85O0.74.504.755.005.255.50SUPPLYVOLTAGE(V)03J–PLD–7/05

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13.ATF16V8B Ordering Information

13.1

tPD(ns)

ATF16V8B Standard Package Options

tS(ns)

tCO(ns)

Ordering CodeATF16V8B-10JCATF16V8B-10PCATF16V8B-10SCATF16V8B-10XCATF16V8B-10JIATF16V8B-10PIATF16V8B-10SIATF16V8B-10XIATF16V8B-15JCATF16V8B-15PCATF16V8B-15SC

Package20J20P320S20X20J20P320S20X20J20P320S20X20J20P320S20X

Operation RangeCommercial(0°C to 70°C)

107.57

Industrial(-40°C to 85°C)

Commercial(0°C to 70°C)

151210

ATF16V8B-15XCATF16V8B-15JIATF16V8B-15PIATF16V8B-15SIATF16V8B-15XI

Industrial(-40°C to 85°C)

Note:The last time buy date is Sept. 30, 2005 for shaded parts.

13.2

tPD(ns)10

ATF16V8B Green Package Options (Pb/Halide-free/RoHS Compliant)

tS(ns)7.5

tCO(ns)7

Ordering CodeATF16V8B-10JUATF16V8B-15JUATF16V8B-15PUATF16V8B-15SUATF16V8B-15XU

Package20J20J20P320S20X

Industrial(-40°C to 85°C)Operation Range

151210

13.3Using “C” Product for Industrial

To use commercial product for Industrial temperature ranges, down-grade one speed gradefrom the “I” to the “C” device (7ns “C” = 10 ns “I”) and de-rate power by 30%.

Package Type

20J20P320S20X

20-lead, Plastic J-leaded Chip Carrier (PLCC)

20-lead, 0.300\" Wide, Plastic Dual Inline Package (PDIP)20-lead, 0.300\" Wide, Plastic Gull-wing Small Outline (SOIC)20-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)

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14.ATF16V8BQ/BQL Ordering Information

14.1

tPD(ns)

ATF16V8BQ and ATF16V8BQL Ordering Information

tS(ns)

tCO(ns)

Ordering CodeATF16V8BQ-10JC

Package20J20P320S20X20J20P320S20X20J20P320S20X

Operation RangeCommercial(0°C to 70°C)

107.57

ATF16V8BQ-10PCATF16V8BQ-10SCATF16V8BQ-10XCATF16V8BQL-15JCATF16V8BQL-15PCATF16V8BQL-15SCATF16V8BQL-15XCATF16V8BQL-15JIATF16V8BQL-15PIATF16V8BQL-15SIATF16V8BQL-15XI

151210

Commercial(0°C to 70°C)

Industrial(-40°C to 85°C)

Note:The last time buy date is Sept. 30, 2005 for shaded parts.

14.2

tPD(ns)

ATF16V8BQ and ATF16V8BQL Green Package Options (Pb/Halide-free/RoHS Compliant)

tS(ns)

tCO(ns)

Ordering CodeATF16V8BQL-15JUATF16V8BQL-15PUATF16V8BQL-15SUATF16V8BQL-15XU

Package20J20P320S20X

Operation RangeIndustrial(-40°C to 85°C)

151210

14.3Using “C” Product for Industrial

To use commercial product for Industrial temperature ranges, down-grade one speed gradefrom the “I” to the “C” device (7ns “C” = 10 ns “I”) and de-rate power by 30%.

Package Type

20J20P320S20X

20-lead, Plastic J-leaded Chip Carrier (PLCC)

20-lead, 0.300\" Wide, Plastic Dual Inline Package (PDIP)20-lead, 0.300\" Wide, Plastic Gull-Wing Small Outline (SOIC)20-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)

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15.Packaging Information

15.1

20J – PLCC

1.14(0.045) X 45˚PIN NO. 1IDENTIFIER1.14(0.045) X 45˚0.318(0.0125)0.191(0.0075) eE1BEB1D2/E2D1D AA2A10.51(0.020)MAX45˚ MAX (3X)COMMON DIMENSIONS(Unit of Measure = mm)SYMBOLAA1A2DD1Notes:1.This package conforms to JEDEC reference MS-018, Variation AA. 2.Dimensions D1 and E1 do not include mold protrusion.Allowable protrusion is .010\"(0.254 mm) per side. Dimension D1and E1 include mold mismatch and are measured at the extremematerial condition at the upper or lower parting line.3. Lead coplanarity is 0.004\" (0.102 mm) maximum.EE1D2/E2BB1eMIN4.1912.286 0.50.7798.09.7798.07.3660.6600.330NOM––––––––––1.270 TYPMAX4.5723.048–10.0339.04210.0339.0428.3820.813 0.533Note 2Note 2 NOTE10/04/01 2325 Orchard Parkway San Jose, CA 95131TITLE20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO.20JREV. BR21

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15.220P3 – PDIP

DPIN1E1ASEATING PLANELB1eEBA1CeCeBSYMBOLAA1DEE1BNotes:1.This package conforms to JEDEC reference MS-001, Variation AD. 2.Dimensions D and E1 do not include mold Flash or Protrusion.Mold Flash or Protrusion shall not exceed 0.25 mm (0.010\"). B1LCeBeCCOMMON DIMENSIONS(Unit of Measure = mm)MIN–0.38124.27.620 6.0960.3561.2702.9210.203–0.000NOM––MAX5.334–NOTE– 26.924 Note 2–––––––– 8.255 7.1120.5591.5513.8100.35610.9221.524Note 2 e 2.540 TYP1/23/04 2325 Orchard Parkway San Jose, CA 95131TITLE20P3, 20-lead (0.300\"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO.20P3REV. DR22

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15.3

20S – SOIC

Dimensions in Millimeters and (Inches). Controlling dimension: Inches.JEDEC Standard MS-0130.51(0.020)0.33(0.013)PIN 1 IDPIN 17.60 (0.2992)10.65 (0.419)7.40 (0.2914)10.00 (0.394)1.27 (0.050) BSC13.00 (0.5118)12.60 (0.4961)2.65 (0.1043)2.35 (0.0926)0.30(0.0118)0.10 (0.0040)0º ~ 8º0.32 (0.0125)0.23 (0.0091)1.27 (0.050)0.40 (0.016)10/23/03 2325 Orchard Parkway San Jose, CA 95131TITLE20S, 20-lead, 0.300\" Body, Plastic Gull Wing Small Outline (SOIC)DRAWING NO.20SREV. BR23

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15.420X – TSSOP

Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters.JEDEC Standard MO-153 ACINDEX MARKPIN14.50 (0.177)6.50 (0.256)4.30 (0.169)6.25 (0.246)6.60 (.260)6.40 (.252)1.20 (0.047) MAX0.65 (.0256) BSC0.30 (0.012)0.19 (0.007)0.15 (0.006)0.05 (0.002)SEATINGPLANE0º ~ 8º0.75 (0.030)0.45 (0.018)0.20 (0.008)0.09 (0.004)10/23/03 2325 Orchard Parkway San Jose, CA 95131TITLE20X, (Formerly 20T), 20-lead, 4.4 mm Body Width, Plastic Thin Shrink Small Outline Package (TSSOP)DRAWING NO.20XREV. CR24

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16.Revision History

16.1

03J

1.ATF16V8B-25 JC/PC/SC/XC/JI/PI/SI/XI were obseleted in August 1999

ATF16V8BQL-25 JC/PC/SC/XC/JI/PI/SI/XI were obseleted in August 1999

These devices were removed from Section 13. ”ATF16V8B Ordering Information” on page 19 and Section 14. ”ATF16V8BQ/BQL Ordering Information” on page 20.2.Green Package options added in 2005.

03J–PLD–7/05

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