a
Preliminary Technical Data
FEATURES5.0V Stereo Audio ADCwith 3.3 V Tolerant Digital InterfaceSupports 96 kHz Sample RatesSupports 16/20/24-Bit Word LengthsMultibit Sigma Delta Modulators with“Perfect Differential Linearity Restoration” forReduced Idle Tones and Noise Floor105 dB (typ) Dynamic Range95 dB (typ) S/(THD+N)Supports 256/512 and 768 xFs Master ClocksFlexible Serial Data PortAllows Right-Justified, Left-Justified, I2S-Compatibleand DSP Serial Port ModesCascadable (up to 4 devices) from a single DSPSPORTDevice Control via SPI compatible serial port oroptional control pinsOn-Chip Reference28-Lead SSOP Package.APPLICATIONSProfessional AudioMixing ConsolesMusical InstrumentsDigital Audio Recorders, IncludingCD-R, MD, DVD-R, DAT, HDDHome Theatre SystemsAutomotive Audio SystemsMultimediaStereo Audio, 24-bit,96 kHz, Multi-bit Σ∆ ADCAD1871PRODUCT OVERVIEWThe AD1871 is a stereo audio ADC intended for digital audioapplications requiring high performance analog-to-digitalconversion. It features two 24-bit conversion channels eachwith programmable gain amplifier (PGA), multi-bit sigma-deltamodulator and decimation filters. Each channel provides95 dB of THD+N and 105 db of Dynamic Range makingthe AD1871 suitable for applications such as DigitalAudio Recorders and Mixing Consoles.Each of the AD1871's input channels (Left and Right) can beconfigured as either differential or single-ended (two inputsmuxed with internal single-ended to differential conversion).The input PGA features a gain range of 0 dB to +12 dB insteps of 3 dB.The Σ∆ modulator features a proprietary multi-bitarchitecture which realises optimum performance over an audiobandwidth with standard audio sampling rates of 32 kHz up to96 kHz. The decimation filter response features very-lowpassband ripple and excellent stopband attenuation.The AD1871's audio data interface supports all commoninterface formats such as I2S, Left-Justified, Right-Justified aswell as other modes which allow for convenient hook-up togeneral purpose digital signal processors (DSPs). The AD1871also features an SPI compatible serial control port which allowsfor convenient control of device parameters and functionalitysuch as sample word-width, PGA-settings, interface-modes etc.The AD1871 operates from a single +5V power supply - withoptional digital interfacing capability of +3.3V. It is housed in a28-lead SSOP package and is characterised for operation overthe temperature range -40°C to 105°C.FUNCTIONAL BLOCK DIAGRAMCAPL1 CAPL2 AVDD DVDD ODVDDCASCLRCLKVINLPVINLNAnalogInputBufferMulti-BitΣ∆ModulatorDecimatorDataPortBCLKDOUTDINVREFAD1871AnalogInputBufferFilterEngineClockDividerRESETMCLKCLATCH/(M/S)VINRPVINRNMulti-BitΣ∆ModulatorDecimatorSPIPortCCLK/(256/512)CIN/(DF1)COUT/(DF0)XCTRLCAPR1 CAPR2 AGND DGND1 DGND2REV. PrD 02/2002
IInformation furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog Devices.
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AD1871–SPECIFICATIONSTEST CONDITIONS UNLESS OTHERWISE NOTED+5.0V25°C12.288MHz991.768Hz–0.5dB Full Scale (dBFS) (Differential - PGA/MUX Enabled)Measurement Bandwidth23.2 Hz to 19.998 kHzWord Width24-bitsLoad Capacitance on Digital Outputs100pF2.4VInput Voltage HI (VIH)Input Voltage LO (VIL)0.8VMaster Mode, Data I2S-Justified.Supply VoltagesAmbient TemperatureInput Clock (FCLKIN) [256 ∞ FS]Input SignalANALOG PERFORMANCEMinResolutionDifferential Input - PGA/MUX EnabledDynamic Range (20 Hz to 20 kHz, –60 dB Input)UnweightedA-WeightedSignal to Noise RatioTotal Harmonic Distorton + Noise (THD+N) Input = -20 dBFSSingle-Ended Input - PGA/MUX EnabledDynamic Range (20 Hz to 20 kHz, –60 dB Input)UnweightedA-WeightedSignal to Noise RatioTotal Harmonic Distorton + Noise (THD+N) Input = -20 dBFSDifferential Input - PGA/MUX DisabledDynamic Range (20 Hz to 20 kHz, –60 dB Input)UnweightedA-WeightedSignal to Noise RatioTotal Harmonic Distorton + Noise (THD+N) Input = -20 dBFSDifferential Input - PGA/MUX Enabled - Fs = 96 kHz (AMC = 1)Dynamic Range (20 Hz to 20 kHz, –60 dB Input)UnweightedA-WeightedSignal to Noise RatioTotal Harmonic Distorton + Noise (THD+N) Input = -20 dBFSAnalog Inputs Differential Input Range (± Full Scale)Input Impedance (PGA/MUX)VREFDC AccuracyGain ErrorInterchannel Gain MismatchGain DriftCrosstalk (EIAJ Method)-2.828Typ24MaxUnitBits101105105-95-100dBdBdBdBdB101105105-95-100dBdBdBdBdB101105105-95-100dBdBdBdBdB101105105-95-100+2.82842.25TBD0.01100100dBdBdBdBdBVkΩV%dBppm/°CdB–2–REV. PrD 02/2002
AD1871
LOW PASS DIGITAL FILTER CHARACTERISTICSMinDecimation Factor- FS = 48 kHz- FS = 96 kHzPassband FrequencyStopband FrequencyPassband RippleStopband AttenuationGroup DelayHIGH PASS DIGITAL FILTER CHARACTERISTICSTyp1282024±0.0001120TBDMaxUnitskHzkHzdBdBµsMinPassband FrequencyStopband FrequencyPassband RippleStopband AttenuationGroup DelayTBDTypMaxTBDTBDUnitsHzHzdBdBsTBDTBD–3–REV. PrD 02/2002
AD1871DATA INTERFACE TIMINGMnemonictDBHtDBLtDBPtDLStDDStDDHDescriptionBCLK High WidthBCLK Low WidthBCLK PeriodDelay from LRCLK transition to BCLK highBCLK High PeriodBCLK High PeriodtDBHBCLKMinTypTBDTBDTBDTBDTBDTBDMaxUnitnsnsnsnsnsns tDBP tDBL tDLS LRCLKDOUTLEFT-JUSTIFIEDMODEtDDSMSBMSB-1tDDHtDDSMSBDOUTI2S-JUSTIFIEDMODEtDDHtDDSMSBDOUTRIGHT-JUSTIFIEDMODE8-BIT CLOCKS(24-BIT DATA)12-BIT CLOCKS(20-BIT DATA)16-BIT CLOCKS(16-BIT DATA)tDDSLSBtDDHtDDHFigure Data Interface TimingCONTROL INTERFACE TIMINGMnemonictCCHtCCLtCSUtCHDtCLLtCLHDescriptionCCLK High WidthCCLK Low WidthCDATA Setup TimeCDATA Hold TimeCLATCH Low WidthCLATCH High WidthtCCHMinTypTBDTBDTBDTBDTBDTBDMaxUnitnsnsnsnsnsnsCCLKCLATCHtCCLtCSUtCLLtCLHD07D06D05D04D03D02D01D00CINCOUTD15D14D13D12D11D10D09D08tCHDD09D08D07D06D05D04D03D02D01D00Figure Control Interface Timing–4– REV. PrD 02/2002AD1871DIGITAL I/OMinInput Voltage HI (VIH)Input Voltage LO (VIL)Input Leakage (IIH @ VIH = 5 V)Input Leakage (IIL @ VIL = 0 V)Output Voltage HI (VOH @ IOH = –2 mA)Output Voltage LO (VOL @ IOL = 2 mA)Input CapacitancePOWERTypMax0.81010UnitVVµAµAVVpF2.4ODVDD-0.4V0.415MinSuppliesVoltage, AVDD and DVDDVoltage, ODVDDAnalog CurrentAnalog Current—Power Down (MCLK Running)Digital Current, DVDDDigital Current, ODVDDDigital Current - Power Down (MCLK Running) DVDDDigital Current - Power Down (MCLK Running) ODVDDPower Supply Rejection (See Figure 11)1 kHz 300 mV p-p Signal at Analog Supply Pins20 kHz 300 mV p-p Signal at Analog Supply PinsStopband (>0.55 ∗ FS)—any 300 mV p-p SignalTEMPERATURE RANGETyp534TBD160.5TBDTBDTBDTBDTBDMax5.55.5UnitVVmAµAmAmAµAµAdBdBdB4.52.7MinSpecifications GuaranteedFunctionality GuaranteedStorageNOTESSpecifications subject to change without notice.Typ25Max105150Units°C°C°C-40–65 –5–REV. PrD 02/2002
AD1871
ABSOLUTE MAXIMUM RATINGSMinDVDD to DGND and ODVDD to DGNDAVDD to AGNDDigital InputsAnalog InputsAGND to DGNDReference VoltageSoldering (10 sec)00DGND – 0.3AGND – 0.3–0.3TypMaxUnitsVVVVV°C66DVDD + 0.3AVDD + 0.30.3Indefinite Short Circuit to Ground+300ORDERING GUIDEModelAD1871YRSEVAL-AD1871EBTemperature-40°C to +105°CPackageDescriptionSSOPEvaluation BoardPackageOptionRS-28CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readilyaccumulate on the human body and test equipment and can discharge without detection. Althoughthe AD1871 features proprietary ESD protection circuitry, permanent damage may occur on devicessubjected to high-energy electrostatic discharges. Therefore, proper ESD precautions arerecommended to avoid performance degradation or loss of functionality.Pin Configuration28-Lead Shrink SSOP(RS-28)MCLKCCLK(256/512)/(DF0)/COUT(DF1)/CIN(M/S)/CLATCHDVDDDGNDXCTRLAVDD123456728LRCLK27BCLK26DOUT2524DINRESET22DGNDTOP VIEW8(Not to Scale)21CASC920AD187123ODVDDAGNDVINLN10VINLP11CAPLP12CAPLN13VREF1419VINRN18VINRP17CAPRP16CAPRN15AGND–6–
REV. PrD 02/2002
AD1871
PIN FUNCTION DESCRIPTIONSPin12Input/OutputIIPinNameMCLKCCLK/(256/512)DescriptionMaster Clock. The Master Clock input determines the sample rate of thedevice.MCLK can be 256, 512 or 768 times the sampling frequency.Control Port Bit Clock/Clock Rate Select - This pin has two functions which aredetermined by the level on pin XCTRL. When XCTRL is low, this pin isconfigured as the clock signal for control port data. If XCTRL is high, this pin isused to select between an MCLK of 256*fs (pin low) or 512*fs (pin high)..Control Port Data Out/Data Format Select 0 - This pin has two functions which aredetermined by the level on pin XCTRL. When XCTRL is low, this pin is configured asthe serial data output for control port data readback. If XCTRL is high, this pin is usedas the low bit (DF0) of the Data Format Selection (See section on External Control).Control Port Data Input - This pin has two functions which are determined by the levelon pin XCTRL. When XCTRL is low, this pin is configured as the serial data input forcontrol port data writing. If XCTRL is high, this pin is used as the high bit (DF1) of theData Format Selection (See section on External Control).Control Port Frame Sync/Data Format Select 1 - This pin has two functionswhich are determined by the level on pin XCTRL. When XCTRL is low, this pinis configured as the frame sync (framing signal) for control port data. If XCTRLis high, this pin is used to select between Master (pin low) or Slave (pin high)modes.+5 V Digital Core SupplyDigital GroundExternal Control Enable - This pin is used to select the control mode for the device.When XCTRL is low, control is via the SPI compatible control port (pins CCLK,CLATCH, CIN and COUT). When XCTRL is enabled (high), control of several devicefunctions is possible by hardware pin strapping (pins 256/512, M/S, DF1 andDF0). In external control mode all other functions are in default state (pleaserefer to control register descriptions and External Control section)+5 V Analog SupplyLeft Channel, Negative Input (via MUX/PGA)Left Channel Positive Input (via MUX/PGA)Left External Filter Capacitor 1 (Direct Input to Modulator)Left External Filter Capacitor 2 (Direct Input to Modulator)Reference Voltage Output. It is recommended to connect a capacitor combinationof 10 uF in parallel with 0.1 uF between VREF and AGND (pin 15). (SeeLayout Recommendations).Analog GroundRight External Filter Capacitor 2 (Direct Input to Modulator)Right External Filter Capacitor 1 (Direct Input to Modulator)Right Channel Positive Input (via MUX/PGA)Right Channel Negative Input (via MUX/PGA)Analog GroundCascade Enable - This pin enables cascading of up to 4 AD1871 devices to a single DSPserial port. (See Cascading section)Digital GroundDigital Interface Supply - The digital interface can operate from 3.3V to 5.0V(nominal).ResetSerial Data Input - This pin is used as a serial data input pin when cascading is enabled.Serial Data OutputBit Clock - The Bit Clock is the audio data serial clock and determines the rate of audiodata transfer.Left/Right Clock - This clock, also known as the word clock, determines thesampling rate. It is an output or input depending on the status of Master/Slave.3I/OCOUT/(DF0)4ICIN/(DF1)5ICLATCH/(M/S)678IIIDVDDDGNDXCTRL910111213141516171819202122232425262728IIII/OI/OOII/OI/OIIIIIIII/OOI/OI/OAVDDVINLNVINLPCAPLPCAPLNVREFAGNDCAPRNCAPRPVINRPVINRNAGNDCASCDGNDODVDDRESETDINDOUTBCLKLRCLK–7–REV. PrD 02/2002
AD1871
Group Delay VariationDEFINITIONSDynamic RangeThe ratio of a full-scale input signal to the integratedinput noise in the passband (20 Hz to 20 kHz), expressedin decibels (dB). Dynamic range is measured with a –60dB input signal and is equal to (S/[THD+N]) +60 dB.Note that spurious harmonics are below the noise with a –60 dB input, so the noise level establishes the dynamicrange. The dynamic range is specified with and without anA-Weight filter applied.Signal to (Total Harmonic Distortion + Noise)The difference in group delays at different inputfrequencies.Specified as the difference between largest and thesmallest group delays in the passband, expressed inmicroseconds (µs).GLOSSARYADC - Analog to Digital ConverterDSP - Digital Signal ProcessorIMCLK - Internal master clock signal, used to clock thedecimating filter section (its frequency must be 256*fs).MCLK - External master clock signal applied to the AD1871.Its frequency can be 256, 512 or 768 *fs. MCLK is dividedinternally to give an IMCLK frequency which must be 256*fs.MODCLK - This is the Σ∆ modulator clock which determinesthe sample rate of the modulator. Ideally it should not exceedthe lower of 6.144 MHz or 128*fs. The MODCLK is derivedfrom the IMCLK by a divider which can be selected as /2 or /4.MUX - MultiplexerPGA - Programmable Gain Amplifier(S/(THD + N))The ratio of the root-mean-square (rms) value of the funda-mental input signal to the rms sum of all other spectralcomponents in the passband, expressed in decibels (dB).PassbandThe region of the frequency spectrum unaffected by the attenu-ation of the digital decimator’s filter.Passband RippleThe peak-to-peak variation in amplitude response from equal-amplitude input signal frequencies within the passband,expressed in decibels.StopbandThe region of the frequency spectrum attenuated by the digitaldecimator’s filter to the degree specified by “stopbandattenuation.”Gain ErrorWith a near full-scale input, the ratio of actual output toexpected output, expressed as a percentage.Interchannel Gain MismatchWith identical near full-scale inputs, the ratio of outputs of thetwo stereo channels, expressed in decibels.Gain DriftChange in response to a near full-scale input with a change intemperature, expressed as parts-per-million (ppm) per °C.Midscale Offset ErrorOutput response to a midscale dc input, expressed in least-significant bits (LSBs).Midscale DriftChange in midscale offset error with a change in temperature,expressed as parts-per-million (ppm) per °C.Crosstalk (EIAJ Method)Ratio of response on one channel with a grounded input to afull-scale 1 kHz sine-wave input on the other channel,expressed in decibels.Power Supply RejectionWith no analog input, signal present at the output when a300 mV p-p signal is applied to power supply pins, expressed indecibels of full scale.Group DelayIntuitively, the time interval required for an input pulse toappear at the converter’s output, expressed in milliseconds(ms). More precisely, the derivative of radian phase withrespect to radian frequency at a given frequency.–8–
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AD1871
FUNCTIONAL DESCRIPTIONClocking SchemeThe MCLK pin is the input for the master clock frequency tothe device. Nominally the MCLK frequency will be 256*fs forcorrect operation of the device. However, if the user's MCLK isa multiple of 256*fs (perhaps 512*fs or 768*fs) then it ispossible to divide down the MCLK frequency to a suitableinternal master clock frequency (IMCLK) using the MCLKDivider block as shown in Figure . Thedivide options can be chosen from pass-through (/1), /2 or /3corresponding with 256*fs, 512*fs or 768*fs MCLKsrespectively. The MCLK divider can be controlled using theMCD1-0 bits of Control Register III (see Table ).The resulting internal MCLK (IMCLK) is used to run thedecimating and filtering engine and must be chosen to be at aratio of 256*fs.AMC Bit(Cont Reg I)0/1HPE Bit(Cont Reg I)AnalogInputΣ∆Modulator6.144MHzSincFilter384kHz/768kHzHalf-BandFilters48kHz/96kHzHigh-PassFilter48kHz/96kHzMODCLK6.144MHzIMCLK/2Divider/4IMCLK12.288MHz/24.576MHzMCLKDivider/1/2/3MCLKFigure Clocking Scheme to Modulator and Filter EngineModulatorThe AD1871's analog Σ∆ modulator section comprises asecond-order multi-bit implementation using Analog Device'sproprietary technology for best performance. As shown inFigure , the two analog integrator blocks arefollowed by a flash ADC section which generates the multi-bitsamples. The output of the of the flash ADC, which isthermometer encoded, is decoded to binary for output to thefilter sections and is scrambled for feedback to the twointegrator stages.The modulator is optimsed for operation at a sampling rate of6.144 MHz (which is 128*fs at 48 kHz sampling and *fs at96 kHz sampling). The modulator clock control (AMC bit inControl Register I) is used to select the modulator clock(MODCLK) as a ratio from the IMCLK. The modulatorclock divider options are /2 (default) - for 48 kHz operation -and /4 - for 96 kHz operation.. When operating with anIMCLK of 12.288 MHz, the default divider setting (/2) gives amodulator clock of 6.144 MHz. When operating with anMCLK of 24.576 MHz, the alternate divider setting (/4) givesa modulator clock of 6.144 MHz. (See Figure)If it is required to operate the device at a different outputsample rate than those detailed above - perhaps 44.1 kHz or88.2 kHz - then the decimation filter cut-off characteristics canbe determined from the normalised frequency response plotTPC .–9–REV. PrD 02/2002AD1871
FromAnalogInputSection͐͐FLASHADCTHERMO-METERTOBINARYDECODERDigitalOutput(4-bits/6.144 MHz)SCRAMBLERFEEDBACK DACSFigure Modulator Block DiagramDigital Decimating FiltersThe filtering and decimation of the AD1871's modulator data-stream is implemented in an embedded DSP engine. The firststage of filtering is the Sinc filtering which has selectabledecimation (selected by the modulator clock control bit (AMC- see modulator section above). The default decimation in theSinc stage provides a sample rate reduction of 16 - thiscorresponds with a MODCLK rate of 128*fs. The alternatesetting of the AMC bit gives a Sinc decimation factor of 8 -which corresponds with a MODCLK rate of *fs.. Theoutput of the Sinc decimator stage is at a rate of 8*fs.The filter engine implements two half-band FIR filter sectionsand a sinc compensation stage which together, give a furtherdecimation factor of 8. Please refer to TPC 1 through 4 fordetails of the responses of the Sinc and FIR filter sections. TPC5 gives the composite response of the sinc and FIR filters.High Pass FilterIn differential mode, the VINxP and VINxN input pins areconnected to a pair of inverting amplifiers whose outputs areconnected to the CAPxP and CAPxN pins respectively (seeFigure ).CAPxNVINxPCAPxPVINxNVCMVCMFigure Differential AnalogInputThe AD1871 features an optional high-pass filter section whichprovides the ability of rejecting DC from the outputdatastream. The high-pass filter is enabled by setting bit 8(HPE) of Control Register I to \"1\". Please refer to TPC and TPC for details of the high-pass filter characteristic.ADC CodingIn single-ended mode, either VINxP or VINxN can be selectedas input. The pair of input inverting amplifiers is reconfiguredas a single-ended to differential conversion stage. Again theoutputs of the differential section are connected to pins CAPxPand CAPxN (see Figure ).The ADC's output data stream is in a two's complementencoded format. The word width can be selected from 16-bit,20-bit or 24-bit (see Table and Table). The coding scheme is detailed in Table below.Table CAPxNVINxPCAPxPVINxNVCMVCMCode011111.......1111.......................................000000........0000........................................100000........0001Analog Input SectionLevel+FS0 (Ref Level)-FSFigure Single-endedAnalog InputThe analog input section comprises a differential PGA stage. Itcan also be configured for single-ended inputs, allowing twosuch inputs to be selected via a multiplex switch. The PGA hasfive gain settings (see Table ) rangingfrom 0 dB to 12 dB in 3 dB steps.The analog input section is enabled (powered on) by default onreset. If it is required to bypass the analog input section byusing the modulator input pins (CAPxP and CAPxN) directly,then the analog input section must be powered down by settingbits MER and MEL in Control register III.–10–REV. PrD 02/2002
AD1871
Serial Data InterfaceThe AD1871's serial data interface consists of three pins(LRCLK, BCLK and SDATA). LRCLK is the framing signalfor Left and Right Channel samples and its frequency is equalto the sampling frequency (fs). BCLK is the serial clock used toclock the data samples from the AD1871 and its frequency isequal to *fs (giving 32 BCLK periods for each of the Leftand Right Channels). SDATA outputs the Left and RightChannel sample data coincident with the rising/falling edge ofBCLK.The serial data interface supports all the popular audiointerface standards such as I2S, Left-Justified (LJ) and Right-Justified (RJ) as well as the serial interfaces of modern DSPs.The interface mode is selected by programming the bits DF1-0of Control Register II (See Tables and).The data sample width can be selected from 16, 20 or 24-bitsby programming bits WW1-0 of Control Register II (SeeTables and ).I2S ModeIn I2S mode the data is left-justified, MSB first, with the MSBplaced in the second BCLK period following the transition ofthe LRCLK. A high to low transition of LRCLK signifies thebegining of the Left channel data transfer while a low to hightransition on LRCLK signifies the begining of the RightChannel data transfer (see Figure ).RIGHT CHANNELLRCLKLEFT CHANNELBCLKDOUTMSBMSB-1MSB-2LSB+2LSB+1LSBMSBMSB-1MSB-2LSB+2LSB+1LSBMSBFigure I2S ModeLJ ModeIn LJ mode the data is left-justified, MSB first, with the MSBplaced in the first BCLK period following the transition of theLRCLK. A high to low transition of LRCLK signifies theLRCLKLEFT CHANNELbegining of the Right channel data transfer while a low to hightransition on LRCLK signifies the begining of the Left Channeldata transfer (see Figure ).RIGHT CHANNELBCLKDOUTMSBMSB-1MSB-2LSB+2LSB+1LSBMSBMSB-1MSB-2LSB+2LSB+1LSBMSBMSB-1Figure LJ ModeRJ ModeIn RJ mode the data is right-justified, LSB last, with the LSBplaced in the last BCLK period preceding the transition of theLRCLK. A high to low transition of LRCLK signifies theLRCLKLEFT CHANNELbegining of the Right channel data transfer while a low to hightransition on LRCLK signifies the begining of the Left Channeldata transfer (see Figure ).RIGHT CHANNELBCLKDOUTLSBMSBMSB-1MSB-2LSB+2LSB+1LSBMSBMSB-1MSB-2LSB+2LSB+1LSBFigure RJ Mode–11–REV. PrD 02/2002AD1871
DSP ModeIn DSP mode tthe LRCLK signal becomes a Frame Syncsignal which pulses high for the BCLK period prior to the MSB(or in the BCLK period of the previous LSB - 32 bits). Thedata is left-justified, MSB first, with the MSB placed in theBCLK period following the LRCLK.pulse (see Figure).In I2S and LJ modes, as the data is left-justified, differences indata word-width between the AD1871 and the controller arenot catastrophic as the MSBs are guaranteed to be transferred.There may however, be a slight reduction in performancedepending on the scale of the mismatch. In RJ mode however,differences in word-width between AD1871 and the controllerhave a catastrophic effect on signal performance as the MSBsof each sample may be lost due to the mismatch.LRCLKLEFT CHANNELRIGHT CHANNELBCLKDOUTMSBMSB-1LSB+2LSB+1LSBMSBMSB-1LSB+2LSB+1LSBMSBMSB-1Figure DSP Mode–12–REV. PrD 02/2002
AD1871
Cascade ModeThe AD1871 supports cascading of up to 4 devices in a daisy-chain configuration to the serial port of a DSP. In cascademode, each device loads an internal -bit shift register withthe results of the left and right channel conversions. The -bitregister is split into two sub-frames of 32-bits each; the first forleft channel data and the second for right-channel data. Theresults are left-justified, msb first within the sub-frames and theword-width setting in Control Register II applies. Remainingbits within the sub-frame, beyond the conversion word-widthare set to zero. Please refer to Figure .24-bit Result20-bit Result16-bit Result32-bit Left Sub-Frame24-bit Result20-bit Result16-bit Result32-bit Right Sub-Frame-bit FrameDSP's RX frame sync (RFS0) is connected to the LRCLK pinof all AD1871 devices.The DSP can be master and supply the frame sync and serialclock to the AD1871s or one of the AD1871s can be set asmaster with the DSP and all other AD1871s set to slave. Eachsampling period begins with a frame sync being generated;either by the DSP or one of the AD1871s - depending onMaster/Slave selection. The frame-sync pulse causes eachdevice to load the -bit data I/O register with the left and rightADC results. These results are then clocked towards the DSPwhere they are received in the following order - Device 1 - Left,Device 1 - Right, Device 2 - Left, Device 2 - Right, Device 3 -Left, Device 3 - Right, Device 4 - Left, Device 4 - Right.The DSP's serial port must be programmed to accept 32-bitword lengths regardless of the AD1871 word-length. Thenumber of sample words to be accepted per sample interval willbe determined by the number of AD1871 devices in cascade -up to a maximum of 8 words corresponding with the maximumnumber of 4 devices.Figure also shows the connection of a separateDSP serial port interface to the Control Port (SPI) interface ofthe cascaded AD1871s. Again this cascade is implemented as adaisy chain in this configuration, although it is possible to haveindividual read/write of the AD1871s using separate CLATCHcontrols for each device.The timing relationships of the cascade mode is shown inFigure .Figure DSP ModeUp to 4 devices can be connected in a daisy-chain as shown inFigure . All devices must be set in cascademode by tieing the CASC pin of each device to a logic high.The first device in the chain (device 4) has its DIN pin tied toeither logic high or low. Its DOUT pin is connected to the DINpin of device 3 whose DOUT is in turn connected to the DINpin of device 2. This daisy chaining is continued until theDOUT of device 1 is connected to the DSP's serial port Rxdata line (DR0). The DSP's RX serial clock (RXCLK0) isconnected to the BCLK pin of all AD1871 devices and theDR1DT1TXCLK1/RXCLK1TFS1/RFS1CLATCHCOUTCOUTCCLKCINCOUTLRCLKCLATCHLRCLKCLATCHLRCLKCLATCHCOUTDINCCLKCCLKCCLKBCLKCINCINCINDOUTLRCLKDOUTDOUTBCLKDOUTBCLKBCLKADSP-21065LSHARC DSPAD1871DINAD1871DINAD1871DINAD1871RFS0RXCLK0DR0Figure DSP Mode–13–REV. PrD 02/2002AD1871
CONTROL/STATUS REGISTERSThe AD1871's operating mode is set by programming three,10-bit control registers via an SPI compatible port. Figure shows the typical connectivity between amicrocontroller and the AD1871's Control Port. Table details the format of theAD1871 control words, which are 16-bits wide with a 4-bitaddress field in positions 15 through 12, a Read/Write bit inposition 11, a reserved bit in position 10 and ten bits of registerdata (corresponding to the control register width) in positions 9through 0. The three control words occupy addresses 0000bthrough 0010b in the register map (see Table ).The AD1871 also features two readback (status) registerswhich can be enabled to track the peak reading on each of thechannels (Left and Right). These 10-bit results are read backvia the SPI compatible port in a 16-bit frame similar to that ofthe control words.The SPI compatible control port features four signals(CCLK. CLATCH, CDATA and COUT). TheCLATCH signal is an enable line which must be low toallow communication to or from the Control Port. TheCCLK is the serial clock which clocks-in serial data viathe CDATA pin and clocks-out serial data via the COUTpin. Figure shows details ofthe Control Port timing.Table Register Address MapAddress00000001001000110100Control RegisterControl Register IControl Register IIControl Register IIIPeak Reading Register IPeak Reading Register IITable Control/Status Word Format15-12Address11R/W10Reserved9876543210Control/Status Data Bits (9-0)CCLKCLATCHCINCOUTFigure Writing to register using Control PortD15D14D13D12D11D10D09D08D07D06D05D04D03D02D01D00CCLKCLATCHCINCOUTD15D14D13D12D11D10D09D08D07D06D05D04D03D02D01D00D09D08D07D06D05D04D03D02D01D00Figure Reading from register using Control Port–14–REV. PrD 02/2002
AD1871
Table Control Register I (Address 0000b - Write Only)15-1211109876543210000000PREHPEPDAMCAGL2AGL1AGL0AGR2AGR1AGR09PREPeak Reading Enable (0 = Disabled; 1 = Enabled)8HPEHigh Pass Filter Enable (0 = Disabled; 1 = Enabled)7PDPowerdown Control (1 = Powerdown; 0 = Normal Operation)6AMCADC Modulator Clock (1 = *fs; 0 = 128*fs)5-3AGL2-0Input Gain (Left Channel - See Table )2-0AGR2-0Input Gain (Right Channel - See Table )Control Register IPeak Reading EnableControl Register I contains bit settings for control of analog-The AD1871 has two readback registers which can befront-end gain, modulator clock selection, powerdown control,enabled to store the peak readings of the left and righthigh-pass filtering and peak hold.channel ADC results. To enable the peak readings to beAnalog Gain Controlcaptured, the Peak Reading Enable bit (PRE), bit 9, mustThe AD1871 features an optional analog-front-end withbe set to logical 1. When set to logical 0, the peak readingselectable gain. Gain is selected using 3 control bits for eachcapture is disabled.channel giving 5 separate and independent gain settings on eachchannel. Bits 2 through 0 (AGR2-0) set the analog gain for theRight Channel while bits 5 through 3 (AGL2-0) set the analoggain for the Left Channel. Table shows the analog gain corresponding to the bit settings inAGx2-0.Table Analog Gain SettingsAGx2AGx1AGx0Gain (dB)000000130106011910012101011001110Modulator ClockThe modulator clock can be chosen to be either 128*fs or*fs. The AMC bit (bit 6) is used to select the modulator'sclock rate. When AMC is set to 0 (default) the modulator clockis 128*fs. Otherwise, if set to 1, the modulator clock is *fs..This bit is normally set depending on whether the desiredsampling frequency is 48 kHz or 96 kHz and is also influencedby the selected MCLK frequency. Please refer to theFunctional Description section for more information on MCLKselection and sampling rates.PowerdownPowerdown of the active clock signals within the AD1871 iseffected by writing a logical 1 to bit 7 (PD).High Pass FilterThe AD1871's digital filtering engine allows the insertion of ahigh pass filter (HPF) to effectively block DC signals from theoutput digital waveform. Setting bit 8 (HPE) enables the high-pass filter. For more details of the HPF, refer to the FunctionalDescription.REV. PrD 02/2002–15–AD1871
Table Control Register II (Address 0001b - Write Only)15-1211000101009-9-76-54-32108--DF1-0WW1-0M/SMURMUL7-6DF15DF04WW13WW02M/S1MUR0MULReservedData Format (See Table ___)Word Width (See Table ___)Master/Slave Select (0 = Master Mode; 1 = Slave Mode)Mute Control - Right Channel (0 = Disabled; 1 = Enabled)Mute Control - Left Channel (0 = Disabled; 1 = Enabled)Control Register IIControl Register II contains bit settings for control of left/right channel muting, data sample word-width, datainterface format, direct modulator bitstream output andmodulator dither enable.Mute Controlinterface format (mode) as shown in Table.Table Data Interface Format SettingsDF10011DF00101InterfaceModeI2SRJDSPLJThe left and right data channels can be muted to digital zero bysetting the MUL and MUR bits (bits 0 and 1) respectively. If achannel is muted its output data stream will remain at digitalzero, regardless of the amplitude of the input signal. Setting thebit to 1 mutes the channel while setting the bit to 0 restoresnormal operation.Master/Slave SelectPlease refer to the section on the Serial Interface in the FunctionalDescription for more details on the various interface modes.The AD1871 can operate as either a slave device or a masterdevice. In slave mode, the controller must provide the LRCLKand BCLK to determine the sample rate and serial bit rate. Inmaster mode, the AD1871 provides the LRCLK and BCLK asoutputs which are applied to the controller. The AD1871defaults to master mode (M/S is low) on reset.Word WidthThe AD1871 allows the output sample word-width to beselected from 16, 20 and 24-bits wide. Compact Disc (CD)compatability may require 16-bits while many modern digitalaudio formats require 24-bit sample resolution. Bits WW1-0 areprogrammed to select the word-width. Table details the control register bit settings corresponding to thevarious word-width selections.Table Word-Width SettingsWW10011WW00101Word-Width(No. of bits)242016ReservedData FormatThe AD1871's serial data interface can be configured froma choice of popular interface formats including I2S, LJ, RJor DSP modes. Bits DF1-0 are programmed to select the–16–REV. PrD 02/2002
AD1871
Table Control Register III (Address 0010b - Write Only)15-1211001001009-9-87-65432108-765SEL4SER3MEL2MXL1MER0MXRMCD1MCD0ReservedMCD1-0SELSERMELMXLMERMXR(Should be programmed to 0)Master Clock Divider (See Table )Single-Ended Enable - Left Channel (0 = Differential; 1 = Single-Ended )Single-Ended Enable - Right Channel (0 = Differential; 1=Single-Ended)Mux/PGA Disable - Left Channel (0 = Enabled; 1 = Disabled)Mux Select - Left Channel(0 = VINLP Selected; 1 = VINLN Selected)Mux/PGA Disable - Right Channel (0 = Enabled; 1 = Disabled)Mux Select - Right Channel(0 = VINRP Selected; 1 = VINRN Selected)Single-Ended Mode EnableControl Register IIIControl register III contains bit settings for configurationof the analog input section (both Left and Right channels).Mux EnableThe Mux Enable Left (MEL) and Mux Enable Right (MER)are used to enable the analog buffers.When these bits are set to1, the analog input buffers are powered-down and input signalsmust be applied directly to the modulator inputs via theCAPxP and CAPxN pins. (See Figure <>). When MEL andMER are set to 0 (default condition after reset), the analoginput section is enabled (See Table ).Table Mux Control SettingsThe Single-Ended Mode Enable bits (SEL and SER forLeft and Right channels respectively), when set to 1 areused to configure single-ended input on VINxP andVINxN (input is selected by state of MXL and MXR. Inthis mode, single-ended inputs taken from either VINxPor VINxN (selected using the Mux Select bits - MXL,MXR) are internally converted to a differential format tobe applied to the modulator section.(See Table).Table Differential/Single-Ended SelectMEL01XXMux SelectMERXX01InputSettingLeft Channel Analog Buffer EnabledLeft Channel Analog Buffer DisabledRight Channel Analog Buffer EnabledRight Channel Analog Buffer DisabledSEL01XXSERXX01InputSettingLeft Channel Input -> DifferentialLeft Channel Input -> Single-EndedRight Channel Input -> DifferentialRight Channel Input -> Single-EndedMaster Clock DividerThe Mux select bits (MXL and MXR for Left and Rightchannels respectively) are used to select the input from VINxPor VINxN when the input is configured as single-ended. WhenMXx is set to 0, the input is taken from VINxP. When MXx isset to 1, the input is taken from VINxN (See Table).Table Mux Select Settings*The Master Clock Divider allows the division of the externalMCLK frequency to a more suitable internal master clockfrequency (IMCLK). IMCLK must be 256*fs, therefore if theavailable MCLK is not at 256*fs, but is a multiple of this, theMCD allows conversion of MCLK to a suitable IMCLK at256*fs. (See Table .)Table Master ClockDivider SettingsMXL01XX*MXRXX01InputSettingLeft Channel Input from VINLPLeft Channel Input from VINLNRight Channel Input from VINRPRight Channel Input from VINRNMCD1MCD000110101MCLKDivisionIMCLK = MCLK (/1)IMCLK = MCLK/2IMCLK = MCLK/3IMCLK = MCLK (/1) Mux Select Settings are only valid when single-ended operation is enabled -SEL and SER are set to 1.–17–REV. PrD 02/2002AD1871
Table Peak Reading Register I (Address 0011b - Read Only)15-1211001111009-9-65-08-7-6-5A0P54A0P43A0P32A0P21A0P10A0P0Reserved (Always set to zero)A0P5-0Left Channel Peak Reading (Valid only when PRE = 1)Table Peak Reading Register II (Address 0100b - Read Only)15-1211010011009-9-65-08-7-6-5A1P54A1P43A1P32A1P21A1P10A1P0Reserved (Always set to zero)A1P5-0Right Channel Peak Reading (Valid only when PRE = 1)Peak Reading RegistersThe Peak Reading Registers are read-only registers whichcan be enabled to track and hold the peak ADC readingfrom each channel. The peak reading feature is enabled bysetting bit PRE in Control Register I. The peak readingvalue is contained in the 6-LSBs of the 10-bit readbackword. The result is binary coded where each LSB isequivalent to -1dbFS with all zeros corresponding to full-scale (0 dbFS) and all ones corresponding to -63 dBFS.(see Table ).Table Peak Reading Result FormatAxP5000...11Code4321000...11000...11000...11001...110010...01Level0 dBFS-1 dBFS-2 dBFS...-62 dBFS-63 dBFSA Peak Reading register read cycle is detailed in Figure.–18–REV. PrD 02/2002
AD1871
EXTERNAL CONTROLThe AD1871, can be configured for external hardwarecontrol of a subset of device functionality. Thisfunctionality includes Master/Slave mode select, MCLKselect and serial Data Format select. External control isenabled by tieing the XCTRL pin high as shown inFigure .AD1871256/512VDDXCTRLDF0DF1M/SFigure External Control ConfigurationMaster/Slave SelectThe Master/Slave hardware select (pin 27 - CIN/(M/S))isequivalent to setting the M/S bit of Control Register II. Ifset low, the device is placed in master mode, whereby theLRCLK and BCLK signals are outputs from the AD1871.When M/S is set high, the device is in slave mode, whereby theLRCK and BCLK signals must be provided as inputs to theAD1871.MCLK Mode SelectThe MCLK Mode hardware select (pin 2 - CCLK/(256/512)) is a subset of the MCLK Mode selection which isdetermined by bits CM1-0 of Control Register II. Whenthe hardware pin is low, the device operates with anMCLK which is 256*fs; while if the pin is set high, thedevice operates with an MCLK which is 512*fs.Serial Data Format SelectThe Serial Data Format hardware select (pins 6,7 - CLATCH/(DF1),COUT/(DF0))is equivalent to setting the bits DF1-0 ofControl Register II.–19–REV. PrD 02/2002AD1871
TYPICAL PERFORMANCE CURVESFilter Responses0−20−40−60−80−100−120−140−1600510Frequency − Normalised to fs15Magnitude − dBMagnitude − dB0−20−40−60−80−100−120−140−1600510Frequency − Normalised to fs15TPC Sinc Filter Response (AMC = 0)TPC Second Halfband FilterResponse00−20−40Magnitude − dB−60−80−100−120−140−1600510Frequency − Normalised to fs15Magnitude − dB−50−100−1500510Frequency − Normalised to fs15TPC First Halfband Filter ResponseTPC Composite Filter Response(AMC = 0)00−20−40Magnitude − dBMagnitude − dB0510Frequency − Normalised to fs15−60−80−100−120−140−160−50−100−15000.511.5Frequency − Normalised to fs2TPC Comb Compensation FilterResponseTPC Composite FilterResponse (Passband Section)(AMC = 0)–20–REV. PrD 02/2002
AD1871Device Performance CurvesTPC High Pass Filter Response - fS = 48 kHzTPC <> 1 kHz Tone at -0.5 dBFS, (32k-point FFT), Fs = 48kHzTPC High Pass Filter Response - fS = 96 kHzTPC <> 1 kHz Tone at -20 dBFS, (32k-point FFT), Fs = 48kHzTPC <> 1 kHz Tone at -60 dBFS, (32k-point FFT), Fs = 48kHz–21–REV. PrD 02/2002AD1871
TPC <> THD+N versus Input Amplitude at 1 kHz, Fs = 48kHzTPC <> THD+N versus Input Frequency at -0.5 dBFS, Fs =48 kHzTPC <> Channel Seperation versus Frequency at -0.5dBFS, Fs = 48 kHz–22–
REV. PrD 02/2002
AD1871
INTERFACINGAnalog InterfacingPGA Input - Single-EndedThe analog section of the AD1871 has been designed to offerflexibility as well as high performance. Users may choose fulldifferential input directly to the ADC's Σ∆ modulator via pinsCAPxP and CAPxN. Alternatively, when using the on-chipPGA section, it is also possible to multiplex single-ended inputson pins VINxP and VINxN or to use these pins for fulldifferential input.Whichever input topology is chosen (direct or via mux/PGAsection), the modulator input pins (CAPxP and CAPxN)require capacitors to act as dynamic charge storage for theswitched capacitor input section. Component selection forthese capacitors is critical as the input audio signal appears onor across these capacitors. A high quality dielectric isrecommened for these capacitors multi-layer ceramic - NPO ormetal film - PPS for surface mounted versions andpolypropylene for through-hole versions. Indeed, as a generalrecommendation, high-quality dielectrics should be specifiedwhere capacitors are carrying the input audio signal.Modulator Direct InputFigure shows connection of asingle-ended source to the PGA section of the AD1871. ThePGA section is configured for Single-Ended to Differentialconversion. The differential outputs are connected internally tothe CAPxx pins via 250Ω series resistors.In order to configure the AD1871 for single-ended input , thecontrol registers must be configured as follows:Left Channel:Control Register I = xx0xGGGxxxwhere GGG = Input Gain (see Table Control Register III = 00xx1x0Sxxwhere S = SE Channel SelectionRight Channel:Control Register I = xx0xxxxGGGwhere GGG = Input Gain (see Table Control Register III = 00xxx1xx0Swhere S = SE Channel SelectionCAPLN1nFNPO100pFNPOCAPLP1nFNPOFigure shows connection of asingle-ended source; via an external single-ended to differentialconverter; to the modulator input of the AD1871. The externalamplifier/buffer should have good slewing characteristics tomeet the dynamic characteristics of the modulator input whichis a switched-capacitor load.The output of the external amplifier/buffer should bedecoupled from the input capacitors via a 250Ω resistor (metalfilm).In order to configure the AD1871 for differential input viaCAPxP and CAPxN pins , the Mux/PGA section must bedisabled by setting the MEL and MER bits in Control RegisterIII to \"1\".120pFNPO5k76OP275237100pFNPOOP2755k76750k2371nFNPOCAPLP1nFNPOCAPLNFerrite600ZAD187110µFVINLP100pFNPO10µF100nFVINLNVREFFigure Single-Ended Inputvia PGA SectionFerrite10µF100pFNPO5k765k76AD1871VREF10µF100nFFigure Direct Connection toModulator–23–REV. PrD 02/2002AD1871
PGA Input - DifferentialFigure shows connection ofa differential source to the PGA section of the AD1871. ThePGA section is configured as a differential buffer. The buffereddifferential outputs are connected internally to the CAPxx pinsvia 250Ω series resistors.In order to configure the AD1871 for differential input via theMux/PGA , the control registers must be configured as follows:Left Channel:Control Register I = xx0xGGGxxxwhere GGG = Input Gain (see Table Control Register III = 00xx0x0xxxRight Channel:Control Register I = xx0xxxxGGGwhere GGG = Input Gain (see Table Control Register III = 00xxx0xx0xCAPLN1nFNPO100pFNPOCAPLP1nFNPOAD187110µF2VINLP3110µFVINLNVREF10µF100nFFigure Differential Inputvia PGA Section–24–REV. PrD 02/2002
AD1871
LAYOUT CONSIDERATIONSIn order to operate the AD1871 at its specified performancelevel, careful consideration must be given to the layout of theAD1871 and its ancillary circuits. Since the analog inputs tothe AD1871 are differential, the voltages in the analogmodulator are common-mode voltages. The excellentcommon-mode rejection of the part will remove common-modenoise on these inputs. The analog and digital supplies of theAD1871 are independent and separately pinned out tominimize coupling between analog and digital sections of thedevice. The digital filters will provide rejection of broadbandnoise on the power supplies, except at integer multiples of themodulator sampling frequency. The digital filters also removenoise from the analog inputs provided the noise source doesnot saturate the analog modulator. However, because theresolution of the AD1871’s ADC is high, and the noise levelsfrom the AD1871 are so low, care must be taken with regard togrounding and layout.The printed circuit board that houses the AD1871 should bedesigned so the analog and digital sections are separated andconfined to certain sections of the board. The AD1871 pinselection has been configued such that its analog and digitalinterfaces are connected on opposite ends of the package. Thisfacilitates the use of ground planes that can be easily separated.A minimum etch technique is generally best for ground planesas it gives the best shielding. Figure is a composite view ofthe solder and component layers of a two-sided PCB layout.The separation between the analog and digital groundplanes(on the solder side) and the analog and digital powerplanes (on the component side) can be seen on the figure.on the power supply lines. Fast switching signals such as clocksshould be shielded with digital ground to avoid radiating noiseto other sections of the board, and clock signals should neverbe run near the analog inputs. Traces on opposite sides of theboard should run at right angles to each other. This will reducethe effects of feedthrough through the board. A microstriptechnique is by far the best but is not always possible with adouble-sided board. In this technique, the component side ofthe board is dedicated to ground planes while signals are placedon the other side.Figure Connecting Analogand Digital GroundsGood decoupling is important when using high speed devices.All analog and digital supplies should be decoupled to AGNDand DGND respectively, with 0.1 µF ceramic capacitors inparallel with 10 µF tantalum capacitors. To achieve the bestfrom these decoupling capacitors, they should be placed asclose as possible to the device, ideally right up against it., asshown in Figure In systemswhere a common supply voltage is used to drive both theAVDD and DVDD of the AD1871, it is recommended that thesystem’s AVDD supply be used. This supply should have therecommended analog supply decoupling between the AVDDpins of the AD1871 and AGND and the recommended digitalsupply decoupling capacitors between the DVDD pin andDGND.Figure GroundLayoutNOTE In the above figure, the black area represents the solder side of the layout,while grey represents the component side of the layout. The silkscreen in whiteis included for clarity Digital and analog ground planes should be joined in only oneplace. If this connection is close to the device, it isrecommended to use a ferrite bead inductor as shown in Figure. The pads for the ferrite arepositioned on the solder-side directly underneath the AD1871device (U1 in the Figure).Avoid running digital lines under the device as they may couplenoise onto the die. The analog ground plane should be allowedto run under the AD1871 to avoid noise coupling. If it is notpossible to use a power supply plane then the power supplylines to the AD1871 should use as large a trace as possible toprovide low impedance paths and reduce the effects of glitchesFigure AD1871 Power SupplyDecouplingAnother important consideration is the selection of componentssuch as capacitors, resistors and operational amplifiers for theancillary circuits–25–REV. PrD 02/2002 AD1871Contents
PRODUCT OVERVIEW
1
AD1871–SPECIFICA-TIONS2
TEST CONDITIONS UNLESS OTHERWISE NOTED
2
ANALOG PERFORMANCE
2
LOW PASS DIGITAL FILTER CHARACTERISTICS
2
HIGH PASS DIGITAL FILTER CHARACTERISTICS
2
DATA INTERFACE TIMING
3
CONTROL INTERFACE TIMING
3
DIGITAL I/O
4POWER
4
TEMPERATURE RANGE
4
ABSOLUTE MAXIMUM RATINGS
5
DEFINITIONS
7
GLOSSARY
7
Modulator
8
FUNCTIONAL DESCRIPTION
8
Clocking Scheme
8
Digital Decimating Filters
9
High Pass Filter
9
ADC Coding
9
Analog Input Section
9
Serial Data Interface
10
CONTROL/STATUS REGISTERS
14
Control Register I
15
Control Register II
16
Control Register III
17
Peak Reading Registers
18
EXTERNAL CONTROL
19
Master/Slave Select
19
MCLK Mode Select
19
Serial Data Format Select
19
TYPICAL PERFORMANCE CURVES
20
Filter Responses
20
Performance Curves
21
INTERFACING
22
Analog Interfacing
22
LAYOUT CONSIDERATIONS
24
OUTLINE DIMENSIONS
26
–26–
REV. PrD 02/2002
AD1871
OUTLINE DIMENSIONSDimensions shown in inches and (mm).28-Lead Shrink Small Outline IC (RS-28)0.407 (10.34)0.397 (10.08)2815REV. PrD 02/2002
1140.078 (1.98)PIN 10.07 (1.79)0.068 (1.73)0.066 (1.67)0.008 (0.203)0.02560.015 (0.38)8¡0.03 (0.762)0¡0.022 (0.558)0.002 (0.050)(0.65)BSC0.010 (0.25)SEATINGPLANE0.009 (0.229)0.005 (0.127)–27–
