4Gb: x8, x16 Automotive DDR4 SDRAM
WRITE Operation
5.CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.6.tCCD_S/L = 5 isn’t allowed in 2tCK preamble mode.
7.The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T20.
8.When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to avalue at least 1 clock greater than the lowest CWL setting supported in the applicabletCK range, which means CWL = 9 is not allowed when operating in 2tCK WRITE pream-ble mode.
Figure 176: WRITE (BC4) OTF to WRITE (BC4) OTF with 1tCK Preamble in Different Bank Group
T0CK_cCK_tT1T2T3T4T7T8T9T10T11T12T13T14T15T16T17T18T19CommandWRITEDESDESDESWRITEDESDESDESDESDESDESDESDESDESDESDESDEStWRDEStCCD_S = 44 ClocksBGbtWTRBank Group
Address
BGaAddress
BankCol nBankCol btWPREtWPSTtWPREtWPSTDQS_t,DQS_cWL = AL + CWL = 9DQ
DInDIn + 1DIn + 2DIn + 3DIbDIb + 1DIb + 2DIb + 3WL = AL + CWL = 9Time Break Transitioning DataDon’t CareNotes:
1.BC4, AL = 0, CWL = 9, Preamble = 1tCK.
2.DI n (or b) = data-in from column n (or column b).
3.DES commands are shown for ease of illustration; other commands may be valid atthese times.
4.BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 andT4.
5.CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.6.The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T17.
4Gb: x8, x16 Automotive DDR4 SDRAM
WRITE Operation
Figure 177: WRITE (BC4) OTF to WRITE (BC4) OTF with 2tCK Preamble in Different Bank Group
T0CK_cCK_tT1T2T3T4T7T8T9T10T11T12T13T14T15T16T17T18T19CommandWRITEDESDESDESWRITEDESDESDESDESDESDESDESDESDESDESDESDESDEStWRtCCD_S = 44 ClocksBGbtWTRBank Group
Address
BGaAddress
BankCol nBankCol btWPREtWPREtWPSTDQS_t,DQS_cWL = AL + CWL = 10DQ
DInDIn + 1DIn + 2DIn + 3DIbDIb + 1DIb + 2DIb + 3WL = AL + CWL = 10Time Break Transitioning DataDon’t CareNotes:
1.BC4, AL = 0, CWL = 9 + 1 = 10 (see Note 7), Preamble = 2tCK.2.DI n (or b) = data-in from column n (or column b).
3.DES commands are shown for ease of illustration; other commands may be valid atthese times.
4.BC4 setting activated by MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 andT4.
5.CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.6.The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T18.
7.When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a
value at least 1 clock greater than the lowest CWL setting supported in the applicabletCK range, which means CWL = 9 is not allowed when operating in 2tCK WRITE pream-ble mode.
Figure 178: WRITE (BC4) Fixed to WRITE (BC4) Fixed with 1tCK Preamble in Different Bank Group
T0CK_cCK_tT1T2T3T4T7T8T9T10T11T12T13T14T15T16T17T18T19CommandWRITEDESDESDESWRITEDESDESDESDESDESDESDESDESDESDESDEStWRDESDEStCCD_S = 42 ClocksBGbtWTRBank Group
Address
BGaAddress
BankCol nBankCol btWPREtWPSTtWPREtWPSTDQS_t,DQS_cWL = AL + CWL = 9DQ
DInDIn + 1DIn + 2DIn + 3DIbDIb + 1DIb + 2DIb + 3WL = AL + CWL = 9Time Break Transitioning DataDon’t CareNotes:
1.BC4, AL = 0, CWL = 9, Preamble = 1tCK.
2.DI n (or b) = data-in from column n (or column b).
4Gb: x8, x16 Automotive DDR4 SDRAM
WRITE Operation
3.DES commands are shown for ease of illustration; other commands may be valid at
these times.
4.BC4 (fixed) setting activated by MR0[1:0] = 10.
5.CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.6.The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T15.
Figure 179: WRITE (BL8) to WRITE (BC4) OTF with 1tCK Preamble in Different Bank Group
T0CK_cCK_tT1T2T3T4T7T8T9T10T11T12T13T14T15T16T17T18T19CommandWRITEDESDESDESWRITEDESDESDESDESDESDESDESDESDESDESDESDEStDESWRtCCD_S = 4BGb4 ClockstWTRBank Group
Address
BGaAddress
BankCol nBankCol btWPREtWPSTDQS_t,DQS_cWL = AL + CWL = 9DQ
DInDIn + 1DIn + 2DIn + 3DIn + 4DIn + 5DIn + 6DIn + 7DIbDIb + 1DIb + 2DIb + 3WL = AL + CWL = 9Time Break Transitioning DataDon’t CareNotes:
1.BL = 8/BC = 4, AL = 0, CL = 9, Preamble = 1tCK.2.DI n (or b) = data-in from column n (or column b).
3.DES commands are shown for ease of illustration; other commands may be valid atthese times.
4.BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during WRITE command at T0.BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T4.
5.CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Disable.6.The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T17.
