ATTINY2313_06资料

Features

•Utilizes the AVR® RISC Architecture

•AVR – High-performance and Low-power RISC Architecture

–120 Powerful Instructions – Most Single Clock Cycle Execution–32 x 8 General Purpose Working Registers–Fully Static Operation

–Up to 20 MIPS Throughput at 20 MHz

Data and Non-volatile Program and Data Memories–2K Bytes of In-System Self Programmable Flash

Endurance 10,000 Write/Erase Cycles

–128 Bytes In-System Programmable EEPROM

•

8-bit Endurance: 100,000 Write/Erase Cycles–128 Bytes Internal SRAM

–Programming Lock for Flash Program and EEPROM Data Security•

Peripheral Features

–One 8-bit Timer/Counter with Separate Prescaler and Compare Mode

–One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Modes–Four PWM Channels

–On-chip Analog Comparator

–Programmable Watchdog Timer with On-chip Oscillator–USI – Universal Serial Interface–Full Duplex USART

•

Special Microcontroller Features–debugWIRE On-chip Debugging

–In-System Programmable via SPI Port–External and Internal Interrupt Sources

–Low-power Idle, Power-down, and Standby Modes–Enhanced Power-on Reset Circuit

–Programmable Brown-out Detection Circuit–Internal Calibrated Oscillator•I/O and Packages

–18 Programmable I/O Lines

–20-pin PDIP, 20-pin SOIC, 20-pad QFN/MLF•Operating Voltages

–1.8 - 5.5V (ATtiny2313V)–2.7 - 5.5V (ATtiny2313)•Speed Grades

–ATtiny2313V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V–ATtiny2313: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V•

Typical Power Consumption–Active Mode

1 MHz, 1.8V: 230 µA

32 kHz, 1.8V: 20 µA (including oscillator)–Power-down Mode

< 0.1 µA at 1.8V

Microcontroller with 2K Bytes In-SystemProgrammable FlashATtiny2313/VPreliminarySummaryRev. 2543IS–AVR–04/06元器件交易网www.cecb2b.com

Pin Configurations

Figure 1. Pinout ATtiny2313

PDIP/SOIC(RESET/dW) PA2(RXD) PD0(TXD) PD1(XTAL2) PA1(XTAL1) PA0(CKOUT/XCK/INT0) PD2(INT1) PD3(T0) PD4(OC0B/T1) PD5GND12345671020191817161514131211VCCPB7 (UCSK/SCL/PCINT7)PB6 (MISO/DO/PCINT6)PB5 (MOSI/DI/SDA/PCINT5)PB4 (OC1B/PCINT4)PB3 (OC1A/PCINT3)PB2 (OC0A/PCINT2)PB1 (AIN1/PCINT1)PB0 (AIN0/PCINT0)PD6 (ICP)MLFPB7 (UCSK/SCK/PCINT7)17 PB6 (MISO/DO/PCINT6)1615 14 13 12 11PA2 (RESET/dW)19 PD0 (RXD)20 (TXD) PD1XTAL2) PA1(XTAL1) PA0(CKOUT/XCK/INT0) PD2(INT1) PD31234518 VCCPB5 (MOSI/DI/SDA/PCINT5)PB4 (OC1B/PCINT4)PB3 (OC1A/PCINT3)PB2 (OC0A/PCINT2)PB1 (AIN1/PCINT1)(T0) PD4(OC0B/T1) PD5NOTE: Bottom pad should be soldered to ground.Overview

The ATtiny2313 is a low-power CMOS 8-bit microcontroller based on the AVRenhanced RISC architecture. By executing powerful instructions in a single clock cycle,the ATtiny2313 achieves throughputs approaching 1 MIPS per MHz allowing the systemdesigner to optimize power consumption versus processing speed.

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(AIN0/PCINT0) PB0GND(ICP) PD6106 7 8 9 元器件交易网www.cecb2b.com

ATtiny2313/V

Block Diagram

Figure 2. Block Diagram

XTAL1PA0 - PA2XTAL2PORTA DRIVERSVCCDATA REGISTERPORTADATA DIR.REG. PORTAINTERNALCALIBRATEDOSCILLATORINTERNALOSCILLATOROSCILLATOR8-BIT DATA BUSGNDPROGRAMCOUNTERSTACKPOINTERWATCHDOG TIMERMCU CONTROLREGISTERMCU STATUSREGISTERTIMING ANDCONTROLRESETPROGRAM FLASHSRAMON-CHIPDEBUGGERINSTRUCTIONREGISTERGENERALPURPOSEREGISTERTIMER/COUNTERSINTERRUPTUNITINSTRUCTIONDECODEREEPROMCONTROLLINESALUUSISTATUSREGISTERPROGRAMMINGLOGICSPIUSARTANALOGCOMPARATORDATA REGISTERPORTBDATA DIR.REG. PORTBDATA REGISTERPORTDDATA DIR.REG. PORTDPORTB DRIVERSPORTD DRIVERSPB0 - PB7PD0 - PD63

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The AVR core combines a rich instruction set with 32 general purpose working registers.All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowingtwo independent registers to be accessed in one single instruction executed in one clockcycle. The resulting architecture is more code efficient while achieving throughputs up toten times faster than conventional CISC microcontrollers.

The ATtiny2313 provides the following features: 2K bytes of In-System ProgrammableFlash, 128 bytes EEPROM, 128 bytes SRAM, 18general purpose I/O lines, 32 generalpurpose working registers, a single-wire Interface for On-chip Debugging, two flexibleTimer/Counters with compare modes, internal and external interrupts, a serial program-mable USART, Universal Serial Interface with Start Condition Detector, a programmableWatchdog Timer with internal Oscillator, and three software selectable power savingmodes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, andinterrupt system to continue functioning. The Power-down mode saves the register con-tents but freezes the Oscillator, disabling all other chip functions until the next interruptor hardware reset. In Standby mode, the crystal/resonator Oscillator is running while therest of the device is sleeping. This allows very fast start-up combined with low-powerconsumption.

The device is manufactured using Atmel’s high density non-volatile memory technology.The On-chip ISP Flash allows the program memory to be reprogrammed In-Systemthrough an SPI serial interface, or by a conventional non-volatile memory programmer.By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a mono-lithic chip, the Atmel ATtiny2313 is a powerful microcontroller that provides a highlyflexible and cost effective solution to many embedded control applications.

The ATtiny2313 AVR is supported with a full suite of program and system developmenttools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Cir-cuit Emulators, and Evaluation kits.

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ATtiny2313/V

Pin Descriptions

VCCGND

Port A (PA2..PA0)

Digital supply voltage.Ground.

Port A is a 3-bit bi-directional I/O port with internal pull-up resistors (selected for eachbit). The Port A output buffers have symmetrical drive characteristics with both high sinkand source capability. As inputs, Port A pins that are externally pulled low will sourcecurrent if the pull-up resistors are activated. The Port A pins are tri-stated when a resetcondition becomes active, even if the clock is not running.

Port A also serves the functions of various special features of the ATtiny2313 as listedon page 53.

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for eachbit). The Port B output buffers have symmetrical drive characteristics with both high sinkand source capability. As inputs, Port B pins that are externally pulled low will sourcecurrent if the pull-up resistors are activated. The Port B pins are tri-stated when a resetcondition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the ATtiny2313 as listedon page 53.

Port D (PD6..PD0)

Port D is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for eachbit). The Port D output buffers have symmetrical drive characteristics with both high sinkand source capability. As inputs, Port D pins that are externally pulled low will sourcecurrent if the pull-up resistors are activated. The Port D pins are tri-stated when a resetcondition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATtiny2313 as listedon page 56.

RESETReset input. A low level on this pin for longer than the minimum pulse length will gener-ate a reset, even if the clock is not running. The minimum pulse length is given in Table15 on page 34. Shorter pulses are not guaranteed to generate a reset. The Reset Inputis an alternate function for PA2 and dW.

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.XTAL1 is an alternate function for PA0.

Output from the inverting Oscillator amplifier. XTAL2 is an alternate function for PA1.A comprehensive set of development tools, application notes and datasheets are avail-able for downloadon http://www.atmel.com/avr.

XTAL1

XTAL2

Resources

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Register Summary

Address

0x3F (0x5F)0x3E (0x5E)0x3D (0x5D)0x3C (0x5C)0x3B (0x5B)0x3A (0x5A)0x39 (0x59)0x38 (0x58)0x37 (0x57)0x36 (0x56)0x35 (0x55)0x34 (0x54)0x33 (0x53)0x32 (0x52)0x31 (0x51)0x30 (0x50)0x2F (0x4F)0x2E (0x4E)0x2D (0x4D)0x2C (0x4C)0x2B (0x4B)0x2A (0x4A)0x29 (0x49)0x28 (0x48)0x27 (0x47)0x26 (0x46)0x25 (0x45)0x24 (0x44)0x23 (0x43)0x22 (ox42)0x21 (0x41)0x20 (0x40)0x1F (0x3F)0x1E (0x3E)0x1D (0x3D)0x1C (0x3C)0x1B (0x3B)0x1A (0x3A)0x19 (0x39)0x18 (0x38)0x17 (0x37)0x16 (0x36)0x15 (0x35)0x14 (0x34)0x13 (0x33)0x12 (0x32)0x11 (0x31)0x10 (0x30)0x0F (0x2F)0x0E (0x2E)0x0D (0x2D)0x0C (0x2C)0x0B (0x2B)0x0A (0x2A)0x09 (0x29)0x08 (0x28)0x07 (0x27)0x06 (0x26)0x05 (0x25)0x04 (0x24)0x03 (0x23)0x02 (0x22)0x01 (0x21)0x00 (0x20)

Name

SREGReservedSPLOCR0BGIMSKEIFRTIMSKTIFRSPMCSROCR0AMCUCRMCUSRTCCR0BTCNT0OSCCALTCCR0ATCCR1ATCCR1BTCNT1HTCNT1LOCR1AHOCR1ALOCR1BHOCR1BLReservedCLKPRICR1HICR1LGTCCRTCCR1CWDTCSRPCMSKReservedEEAREEDREECRPORTADDRAPINAPORTBDDRBPINBGPIOR2GPIOR1GPIOR0PORTDDDRDPINDUSIDRUSISRUSICRUDRUCSRAUCSRBUBRRLACSRReservedReservedReservedReservedUCSRCUBRRHDIDRReserved

Bit 7

I–SP7INT1INTF1TOIE1TOV1–PUD–FOC0A–COM0A1COM1A1ICNC1

Bit 6

T–SP6INT0INTF0OCIE1AOCF1A–SM1–FOC0BCAL6COM0A0COM1A0ICES1

Bit 5

H–SP5PCIEPCIFOCIE1BOCF1B–SE––CAL5COM0B1COM1B1

–

Bit 4

S–SP4––––CTPBSM0––CAL4COM0B0COM1BOWGM13

Bit 3

V–SP3––ICIE1ICF1RFLBISC11WDRFWGM02CAL3––WGM12

Bit 2

N–SP2––OCIE0BOCF0BPGWRTISC10BORFCS02CAL2––CS12

Bit 1

Z–SP1––TOIE0TOV0PGERSISC01EXTRFCS01CAL1WGM01WGM11CS11

Bit 0

C–SP0––OCIE0AOCF0ASELFPRGEN

ISC00PORFCS00CAL0WGM00WGM10CS10

Page

71078606279, 1107915678533777782574105108109109109109110110

Timer/Counter0 – Compare Register B

Timer/Counter0 – Compare Register A

Timer/Counter0 (8-bit)

Timer/Counter1 – Counter Register High ByteTimer/Counter1 – Counter Register Low ByteTimer/Counter1 – Compare Register A High ByteTimer/Counter1 – Compare Register A Low ByteTimer/Counter1 – Compare Register B High ByteTimer/Counter1 – Compare Register B Low Byte

–CLKPCE

––

––

––

–CLKPS3

–CLKPS2

–CLKPS1

–CLKPS0

27110110

Timer/Counter1 - Input Capture Register High ByteTimer/Counter1 - Input Capture Register Low Byte

–FOC1AWDIFPCINT7––––––PORTB7DDB7PINB7

––––PORTB6DDB6PINB6

EEPM1–––PORTB5DDB5PINB5

EEPM0–––PORTB4DDB4PINB4

–FOC1BWDIEPCINT6

–

––WDP3PCINT5–

––WDCEPCINT4

–

––WDEPCINT3

–

EEPROM Address RegisterEEPROM Data Register

EERIE–––PORTB3DDB3PINB3

EEMPEPORTA2DDA2PINA2PORTB2DDB2PINB2

EEPEPORTA1DDA1PINA1PORTB1DDB1PINB1

EEREPORTA0DDA0PINA0PORTB0DDB0PINB0

––WDP2PCINT2–

––WDP1PCINT1–

PSR10–WDP0PCINT0

–

821094262151616585858585858202020

General Purpose I/O Register 2General Purpose I/O Register 1General Purpose I/O Register 0

–––USISIFUSISIERXCRXCIEACD––––––––

PORTD6DDD6PIND6USIOIFUSIOIETXCTXCIEACBG––––UMSEL–––

PORTD5DDD5PIND5USIPFUSIWM1UDREUDRIEACO––––UPM1–––

PORTD4DDD4PIND4USIDCUSIWM0FERXENACI––––UPM0–––

––

––

PORTD3DDD3PIND3USICNT3USICS1DOR

TXEN

UBRRH[7:0]

ACIE––––USBS

PORTD2DDD2PIND2USICNT2USICS0UPEUCSZ2ACIC––––UCSZ1

UBRRH[11:8]

AIN1D–

AIN0D–

PORTD1DDD1PIND1USICNT1USICLKU2XRXB8ACIS1––––UCSZ0

PORTD0DDD0PIND0USICNT0USITCMPCMTXB8ACIS0––––UCPOL

585858145146147130130132134150

USI Data Register

UART Data Register (8-bit)

133134151

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ATtiny2313/V

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ATtiny2313/V

Note:

1.For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.2.I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

3.Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI

instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. TheCBI and SBI instructions work with registers 0x00 to 0x1F only.

4.When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O

Registers as data space using LD and ST instructions, 0x20 must be added to these addresses.

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Instruction Set Summary

Mnemonics

ADDADCADIWSUBSUBISBCSBCISBIWANDANDIORORIEORCOMNEGSBRCBRINCDECTSTCLRSERRJMPIJMPRCALLICALLRETRETICPSECPCPCCPISBRCSBRSSBICSBISBRBSBRBCBREQBRNEBRCSBRCCBRSHBRLOBRMIBRPLBRGEBRLTBRHSBRHCBRTSBRTCBRVSBRVCBRIEBRIDSBICBILSLLSRROL

Rd,RrRd,RrRd,RrRd,KRr, bRr, bP, bP, bs, ks, k k k k k k k k k k k k k k k k k k kP,bP,bRdRdRdk

Operands

Rd, RrRd, RrRdl,KRd, RrRd, KRd, RrRd, KRdl,KRd, RrRd, KRd, RrRd, KRd, RrRdRdRd,KRd,KRdRdRdRdRdk

Add two Registers

Description

Rd ← Rd + Rr

OperationFlags

Z,C,N,V,HZ,C,N,V,HZ,C,N,V,SZ,C,N,V,HZ,C,N,V,HZ,C,N,V,HZ,C,N,V,HZ,C,N,V,SZ,N,VZ,N,VZ,N,VZ,N,VZ,N,VZ,C,N,VZ,C,N,V,HZ,N,VZ,N,VZ,N,VZ,N,VZ,N,VZ,N,VNoneNoneNoneNoneNoneNoneINoneZ, N,V,C,HZ, N,V,C,HZ, N,V,C,HNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneZ,C,N,VZ,C,N,VZ,C,N,V

#Clocks

11211112111111111111112233441/2/31 111/2/31/2/31/2/31/2/31/21/21/21/21/21/21/21/21/21/21/21/21/21/21/21/21/21/21/21/222111

ARITHMETIC AND LOGIC INSTRUCTIONS

Add with Carry two RegistersAdd Immediate to WordSubtract two Registers

Subtract Constant from Register Subtract with Carry two RegistersSubtract with Carry Constant from Reg.Subtract Immediate from WordLogical AND Registers

Logical AND Register and ConstantLogical OR Registers

Logical OR Register and ConstantExclusive OR RegistersOne’s ComplementTwo’s ComplementSet Bit(s) in RegisterClear Bit(s) in RegisterIncrementDecrement

Test for Zero or MinusClear RegisterSet RegisterRelative JumpIndirect Jump to (Z)Relative Subroutine Call Indirect Call to (Z)Subroutine ReturnInterrupt ReturnCompare, Skip if EqualCompare

Compare with Carry

Compare Register with ImmediateSkip if Bit in Register ClearedSkip if Bit in Register is SetSkip if Bit in I/O Register ClearedSkip if Bit in I/O Register is SetBranch if Status Flag SetBranch if Status Flag ClearedBranch if Equal Branch if Not EqualBranch if Carry SetBranch if Carry ClearedBranch if Same or Higher Branch if LowerBranch if MinusBranch if Plus

Branch if Greater or Equal, SignedBranch if Less Than Zero, SignedBranch if Half Carry Flag SetBranch if Half Carry Flag ClearedBranch if T Flag SetBranch if T Flag ClearedBranch if Overflow Flag is SetBranch if Overflow Flag is ClearedBranch if Interrupt EnabledBranch if Interrupt DisabledSet Bit in I/O RegisterClear Bit in I/O RegisterLogical Shift LeftLogical Shift RightRotate Left Through Carry

Rd ← Rd + Rr + CRdh:Rdl ← Rdh:Rdl + KRd ← Rd - RrRd ← Rd - KRd ← Rd - Rr - CRd ← Rd - K - CRdh:Rdl ← Rdh:Rdl - KRd ← Rd • RrRd ← Rd • KRd ← Rd v RrRd ← Rd v KRd ← Rd ⊕ RrRd ← 0xFF − RdRd ← 0x00 − RdRd ← Rd v K

Rd ← Rd • (0xFF - K)

Rd ← Rd + 1

Rd ← Rd − 1 Rd ← Rd • Rd Rd ← Rd ⊕ RdRd ← 0xFFPC ← PC + k + 1PC ← Z PC ← PC + k + 1PC ←ZPC ← STACKPC ← STACK

if (Rd = Rr) PC ← PC + 2 or 3Rd − RrRd − Rr − CRd − K

if (Rr(b)=0) PC ← PC + 2 or 3 if (Rr(b)=1) PC ← PC + 2 or 3if (P(b)=0) PC ← PC + 2 or 3 if (P(b)=1) PC ← PC + 2 or 3if (SREG(s) = 1) then PC←PC+k + 1if (SREG(s) = 0) then PC←PC+k + 1if (Z = 1) then PC ← PC + k + 1if (Z = 0) then PC ← PC + k + 1if (C = 1) then PC ← PC + k + 1if (C = 0) then PC ← PC + k + 1if (C = 0) then PC ← PC + k + 1if (C = 1) then PC ← PC + k + 1if (N = 1) then PC ← PC + k + 1if (N = 0) then PC ← PC + k + 1if (N ⊕ V= 0) then PC ← PC + k + 1if (N ⊕ V= 1) then PC ← PC + k + 1if (H = 1) then PC ← PC + k + 1if (H = 0) then PC ← PC + k + 1if (T = 1) then PC ← PC + k + 1if (T = 0) then PC ← PC + k + 1if (V = 1) then PC ← PC + k + 1if (V = 0) then PC ← PC + k + 1if ( I = 1) then PC ← PC + k + 1if ( I = 0) then PC ← PC + k + 1I/O(P,b) ←1I/O(P,b) ←0

Rd(n+1) ← Rd(n), Rd(0) ← 0Rd(n) ← Rd(n+1), Rd(7) ← 0Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

BRANCH INSTRUCTIONS

BIT AND BIT-TEST INSTRUCTIONS

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ATtiny2313/V

Mnemonics

RORASRSWAPBSETBCLRBSTBLDSECCLCSENCLNSEZCLZSEICLISESCLSSEVCLVSETCLTSEHCLH

DATA TRANSFER INSTRUCTIONSMOVMOVWLDILDLDLDLDLDLDLDDLDLDLDLDDLDSSTSTSTSTSTSTSTDSTSTSTSTDSTSLPMLPMLPMSPMINOUTPUSHPOPNOPSLEEPWDRBREAK

Rd, PP, RrRrRdRd, ZRd, Z+Rd, RrRd, RrRd, KRd, XRd, X+Rd, - XRd, YRd, Y+Rd, - YRd,Y+qRd, ZRd, Z+Rd, -ZRd, Z+qRd, kX, RrX+, Rr- X, RrY, RrY+, Rr- Y, RrY+q,RrZ, RrZ+, Rr-Z, RrZ+q,Rrk, Rr

Rd ← RrRd+1:Rd ← Rr+1:RrCopy Register Word Load ImmediateRd ←K

Load IndirectRd ← (X)Load Indirect and Post-Inc. Rd ← (X), X ← X + 1Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X)

Rd ← (Y)

Load Indirect and Post-Inc.Rd ← (Y), Y ← Y + 1

Load Indirect and Pre-Dec.Y ← Y - 1, Rd ← (Y)Load Indirect

Load Indirect with DisplacementRd ← (Y + q) Load Indirect Rd ← (Z)

Load Indirect and Post-Inc.Rd ← (Z), Z ← Z+1 Load Indirect and Pre-Dec.Z ← Z - 1, Rd ← (Z)Load Indirect with DisplacementLoad Direct from SRAMStore Indirect

Store Indirect and Post-Inc.Store Indirect and Pre-Dec.Store Indirect

Store Indirect and Post-Inc.Store Indirect and Pre-Dec.Store Indirect with DisplacementStore Indirect

Store Indirect and Post-Inc.Store Indirect and Pre-Dec.Store Indirect with DisplacementStore Direct to SRAMLoad Program MemoryLoad Program Memory

Load Program Memory and Post-IncStore Program MemoryIn PortOut Port

Push Register on StackPop Register from StackNo OperationSleep

Watchdog ResetBreak

(see specific descr. for Sleep function)(see specific descr. for WDR/timer)For On-chip Debug OnlyRd ← (Z + q)Rd ← (k)(X) ← Rr

(X) ← Rr, X ← X + 1X ← X - 1, (X) ← Rr(Y) ← Rr

(Y) ← Rr, Y ← Y + 1Y ← Y - 1, (Y) ← Rr(Y + q) ← Rr(Z) ← Rr

(Z) ← Rr, Z ← Z + 1Z ← Z - 1, (Z) ← Rr(Z + q) ← Rr(k) ← RrR0 ← (Z)Rd ← (Z)

Rd ← (Z), Z ← Z+1(Z) ← R1:R0Rd ←PP ← RrSTACK ← RrRd ← STACK

Move Between Registers

NoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNoneNone

111222222222222222222222222333-1122111N/A

Operands

RdRdRdssRr, bRd, b

Arithmetic Shift RightSwap NibblesFlag SetFlag Clear

Description

Rotate Right Through Carry

Operation

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)Rd(n) ← Rd(n+1), n=0..6

Flags

Z,C,N,VZ,C,N,VNoneSREG(s)SREG(s)TNoneCCNNZZIISSVVTTHH

#Clocks

11111111111111111111111

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

SREG(s) ← 1

SREG(s) ← 0 T ← Rr(b)Rd(b) ←TC ←1C ← 0 N ←1N ← 0 Z ←1Z ← 0 I ←1I ← 0 S ←1S ← 0 V ←1V ← 0 T ←1T ← 0

H ←1

H ← 0

Bit Store from Register to TBit load from T to RegisterSet CarryClear CarrySet Negative FlagClear Negative FlagSet Zero FlagClear Zero FlagGlobal Interrupt EnableGlobal Interrupt DisableSet Signed Test FlagClear Signed Test Flag

Set Twos Complement Overflow.Clear Twos Complement OverflowSet T in SREGClear T in SREG

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

MCU CONTROL INSTRUCTIONS

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Ordering Information

Speed (MHz)(3)Power Supply

Ordering CodeATtiny2313V-10PIATtiny2313V-10PU(2)ATtiny2313V-10SIATtiny2313V-10SU(2)ATtiny2313V-10MU(2)ATtiny2313-20PIATtiny2313-20PU(2)ATtiny2313-20SIATtiny2313-20SU(2)ATtiny2313-20MU(2)

Package(1)20P320P320S20S20M120P320P320S20S20M1

Operation Range

Industrial(-40°C to 85°C)

101.8 - 5.5V

202.7 - 5.5V

Industrial(-40°C to 85°C)

Note:

1.This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.2.Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc-tive).Also Halide free and fully Green.

3.For Speed vs. VCC, see Figure 82 on page 181 and Figure 83 on page 181.

Package Type

20P320S20M1

20-lead, 0.300\" Wide, Plastic Dual Inline Package (PDIP)

20-lead, 0.300\" Wide, Plastic Gull Wing Small Outline Package (SOIC)

20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (MLF)

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ATtiny2313/V

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ATtiny2313/V

Packaging Information

20P3

DPIN1E1ASEATING PLANELB1eEBA1CeCeBSYMBOLAA1DEE1BNotes:1.This package conforms to JEDEC reference MS-001, Variation AD. 2.Dimensions D and E1 do not include mold Flash or Protrusion.Mold Flash or Protrusion shall not exceed 0.25 mm (0.010\"). B1LCeBeCCOMMON DIMENSIONS(Unit of Measure = mm)MIN–0.38125.4937.620 6.0960.3561.2702.9210.203–0.000NOM––MAX5.334–NOTE– 25.984 Note 2–––––––– 8.255 7.1120.5591.5513.8100.35610.9221.524Note 2 e 2.540 TYP1/12/04 2325 Orchard Parkway San Jose, CA 95131TITLE20P3, 20-lead (0.300\"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO.20P3REV. CR11

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20S

C1EH NTop ViewA1End ViewCOMMON DIMENSIONS(Unit of Measure = inches)ebADSYMBOLMINL NOMMAXNOTEAA1bCDEHLe0.09260.00400.01300.00910.49610.29140.39400.0160 0.050 BSC0.10430.01180.02000.01250.51180.29920.41900.0503124Side ViewNotes:1.This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AC for additional information.2. Dimension \"D\" does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006\") per side.3.Dimension \"E\" does not include inter-lead Flash or protrusion. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010\") per side.4.\"L\" is the length of the terminal for soldering to a substrate.5.The lead width \"b\1/9/02(0.024\") per side.R2325 Orchard ParkwaySan Jose, CA 95131TITLE20S2, 20-lead, 0.300\" Wide Body, Plastic GullWing Small Outline Package (SOIC)DRAWING NO.20S2REV. A12

ATtiny2313/V

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ATtiny2313/V

20M1

D1Pin 1 ID23ESIDE VIEWTOP VIEWA2D2 A1Pin #1 Notch(0.20 R) 23A10.08CE2SYMBOLCOMMON DIMENSIONS(Unit of Measure = mm)MINNOMMAXNOTEbA 0.70 0.75 0.80A1 – 0.01 0.05LeBOTTOM VIEWA2 0.20 REFb 0.18 0.23 0.30 D 4.00 BSCD2 2.45 2.60 2.75E 4.00 BSCE2 2.45 2.60 2.75e0.50 BSCNote: Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5.L 0.35 0.40 0.55 10/27/04TITLE 2325 Orchard Parkway20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, San Jose, CA 95131 2.6 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO.20M1REV. AR13

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Errata

ATtiny2313 Rev B

The revision in this section refers to the revision of the ATtiny2313 device.••••

Wrong values read after Erase Only operationParallel Programming does not workWatchdog Timer Interrupt disabled

EEPROM can not be written below 1.9 volts

1.Wrong values read after Erase Only operation

At supply voltages below 2.7 V, an EEPROM location that is erased by the EraseOnly operation may read as programmed (0x00).Problem Fix/Workaround

If it is necessary to read an EEPROM location after Erase Only, use an Atomic Writeoperation with 0xFF as data in order to erase a location. In any case, the Write Onlyoperation can be used as intended. Thus no special considerations are needed aslong as the erased location is not read before it is programmed.2.Parallel Programming does not work

Parallel Programming is not functioning correctly. Because of this, reprogrammingof the device is impossible if one of the following modes are selected: ––

In-System Programming disabled (SPIEN unprogrammed)Reset Disabled (RSTDISBL programmed)

Problem Fix/Workaround

Serial Programming is still working correctly. By avoiding the two modes above, thedevice can be reprogrammed serially.3.Watchdog Timer Interrupt disabled

If the watchdog timer interrupt flag is not cleared before a new timeout occurs, thewatchdog will be disabled, and the interrupt flag will automatically be cleared. This isonly applicable in interrupt only mode. If the Watchdog is configured to reset thedevice in the watchdog time-out following an interrupt, the device works correctly.Problem fix / Workaround

Make sure there is enough time to always service the first timeout event before anew watchdog timeout occurs. This is done by selecting a long enough time-outperiod.

4.EEPROM can not be written below 1.9 volts

Writing the EEPROM at VCC below 1.9 volts might fail.Problem fix / Workaround

Do not write the EEPROM when VCC is below 1.9 volts.

ATtiny2313 Rev A

Revision A has not been sampled.

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ATtiny2313/V

Datasheet Revision History

Changes from Rev. 2514H-02/05 to Rev. 2514I-04/06

Please note that the referring page numbers in this section are referred to this docu-ment. The referring revision in this section are referring to the document revision.

1.2.34.5.6.7.8.9.10.11.12.13.14.15.

Updated typos.

Updated Figure 1 on page 2.Added “Resources” on page 6.

Updated “Default Clock Source” on page 25.

Updated “128 kHz Internal Oscillator” on page 30.

Updated “Power Management and Sleep Modes” on page 33

Updated Table 3 on page 25,Table 13 on page 33, Table 14 on page 34,Table 19 on page 45, Table 31 on page 63, Table 79 on page 180.Updated “External Interrupts” on page 62.

Updated “Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0” on page65.

Updated “Bit 6 – ACBG: Analog Comparator Bandgap Select” on page153.

Updated “Calibration Byte” on page 1.Updated “DC Characteristics” on page 181.Updated “Register Summary” on page 6.Updated “Ordering Information” on page 10.

Changed occurences of OCnA to OCFnA, OCnB to OCFnB and OC1x toOCF1x.

Changes from Rev. 2514G-10/04 to Rev. 2514H-02/05

1.2.3.4.5.

Updated Table 6 on page 24, Table 15 on page 34, Table 68 on page 161and Table 80 on page 180.

Changed CKSEL default value in “Default Clock Source” on page 22 to8 MHz.

Updated “Programming the Flash” on page 166, “Programming theEEPROM” on page 168 and “Enter Programming Mode” on page 1.Updated “DC Characteristics” on page 178.

MLF option updated to “Quad Flat No-Lead/Micro Lead Frame(QFN/MLF)”

Changes from Rev. 2514F-08/04 to Rev. 2514G-10/04

1.2.3.4.5.Updated “Features” on page 1.

Updated “Pinout ATtiny2313” on page 2.Updated “Ordering Information” on page 10.Updated “Packaging Information” on page 11.Updated “Errata” on page 14.

Changes from Rev. 2514E-04/04 to Rev. 2514F-08/04

1.2.3.Updated “Features” on page 1.

Updated “Alternate Functions of Port B” on page 53.Updated “Calibration Byte” on page 161.

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4.5.6.7.8.9.10.

Moved Table 69 on page 161 and Table 70 on page 162 to “Page Size”on page 161.

Updated “Enter Programming Mode” on page 1.

Updated “Serial Programming Algorithm” on page 174.Updated Table 78 on page 175.

Updated “DC Characteristics” on page 178.

Updated “ATtiny2313 Typical Characteristics” on page 182.

Changed occurences of PCINT15 to PCINT7, EEMWE to EEMPE andEEWE to EEPE in the document.

Changes from Rev. 2514D-03/04 to Rev. 2514E-04/04

1.

2.3.4.5.

Speed Grades changed- 12MHz to 10MHz- 24MHz to 20MHz

Updated Figure 1 on page 2.

Updated “Ordering Information” on page 10.

Updated “Maximum Speed vs. VCC” on page 181.

Updated “ATtiny2313 Typical Characteristics” on page 182.

Changes from Rev. 2514C-12/03 to Rev. 2514D-03/04

1.2.3.4.5.6.7.8.9.

Updated Table 2 on page 22.

Replaced “Watchdog Timer” on page 39.

Added “Maximum Speed vs. VCC” on page 181.

“Serial Programming Algorithm” on page 174 updated.Changed mA to µA in preliminary Figure 136 on page 208.“Ordering Information” on page 10 updated. MLF package option removed

Package drawing “20P3” on page 11 updated.Updated C-code examples.

Renamed instances of SPMEN to SELFPRGEN, Self ProgrammingEnable.

Changes from Rev. 2514B-09/03 to Rev. 2514C-12/03Changes from Rev. 2514A-09/03 to Rev. 2514B-09/03

1.Updated “Calibrated Internal RC Oscillator” on page 24.

1.2.3.4.5.6.7.8.9.Fixed typo from UART to USART and updated Speed Grades and PowerConsumption Estimates in “Features” on page 1.Updated “Pin Configurations” on page 2.

Updated Table 15 on page 34 and Table 80 on page 180.

Updated item 5 in “Serial Programming Algorithm” on page 174.Updated “Electrical Characteristics” on page 178.

Updated Figure 82 on page 181 and added Figure 83 on page 181.Changed SFIOR to GTCCR in “Register Summary” on page 6.Updated “Ordering Information” on page 10.Added new errata in “Errata” on page 14.

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